Datasheet LT3957A (Analog Devices) - 8

LT3957A
BLOCK DIAGRAM
L1 CDC D1 V t V IN OUT R4 R3 CIN L2 COUT t EN/UVLO VIN SW 25 27 8, 9, 20, A10 21, 38 I – S1 2μA 1.22V + 2.5V INTERNAL REGULATOR AND UVLO CURRENT IS2 LIMIT 10μA UVLO 5.2V LDO M2 Q3 A8 INTVCC 2.5V G4 28 2.7V CVCC IS3 A11 1.72V – TLO 165˚C + DRIVER G6 SR1 A12 VC – – A7 G5 R O G2 M1 + –0.88V + S SENSE1 6 Q2 PWM COMPARATOR RSENSE GND – 48mV 1.6V +A1 A6 12, 13, 14, SLOPE V – + ISENSE 15, 16, 17 SENSE SENSE2 RAMP + + 3 A2 RAMP A5 –0.8V – – GENERATOR 1.28V – +A3 100kHz-1MHz G1 OSCILLATOR 1.2V + FREQUENCY + FOLDBACK A4 Q1 – LOW SIDE FREQ CLAMP PROG FBX VC SS SYNC RT SGND 31 30 32 34 33 4, 23, 3957A F01 R2 24, 37 VOUT C R C C2 C SS RT R1 CC1
Figure 1. LT3957A Block Diagram Working as a SEPIC Converter
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