DATASHEET CD4070BMS, CD4077BMS FN3322 CMOS Quad Exclusive OR and Exclusive NOR Gates Rev 0.00 December 1992 FeaturesPinoutsCD4070BMS TOP VIEW • High Voltage Types (20V Rating)A 114 VDD• CD4070BMS - Quad Exclusive OR GateB 213 H• CD4077BMS - Quad Exclusive NOR GateJ = A B 312 G• Medium Speed OperationK = C D 411 M = G H- tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pFC 510 L = E F• 5V, 10V and 15V Parametric RatingsD 69 FVSS 78 E• Standardized, Symmetrical Output Characteristics• 100% Tested for Quiescent Current at 20VCD4077BMS TOP VIEW • Maximum Input Current of 1 A at 18V Over Full Pack-age Temperature Range; 100nA at 18V and +25oCA 114 VDD• Noise Margin (Over Full Package/Temperature Range)B 213 H- 1V at VDD = 5VJ = A B 312 G- 2V at VDD = 10VK = CÝ D 411 M = G H- 2.5V at VDD = 15VC 510 L = E F• Meets All Requirements of JEDEC Tentative StandardD 69 FNo. 13B, “Standard Specifications for Description ofVSS 78 E‘B’ Series CMOS Devices”ApplicationsFunctional Diagram• Logical Comparators1A3• Parity Generators and Checkers2JBJ = A B• Adders/SubtractorsK = C D5C46KDM = G HDescriptionL = E F8E10 CD4070BMS contains four independent Exclusive OR 9LVSS = 7F gates. The CD4077BMS contains four independent Exclu- VDD = 1412 sive NOR gates. G1113MH The CD4070BMS and CD4077BMS provide the system designer with a means for direct implementation of the Exclusive OR and Exclusive NOR functions, respectively. CD4070BMS The CD4070BMS and CD4077BMS are supplied in these 14 1A3 lead outline packages: 2JB Braze Seal DIP H4Q J = A B5C4K = C D6K Frit Seal DIP H1B D Ceramic Flatpack *H4F †H3W 8M = G HE109L *CD4070B Only †CD4077B Only L = E FF12G1113MHCD4077BMS FN3322 Rev 0.00 Page 1 of 8 December 1992
