Datasheet ADXL346 (Analog Devices) - 9

ADXL346 Data Sheet 60 250 200 50 ) 150 % ( ) g m 100 40 TION T ( A E L 50 PU 30 OFFS 0 PO g F O RO –50 T E 20 Z EN C –100 PER –150 10
010
–200
013
0
08167-
–250
08167-
–3 –2 –1 0 1 –40 –20 0 20 40 60 80 100 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg /°C) TEMPERATURE (°C)
Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V Figure 13. X-Axis Zero g Offset vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V
60 250 200 50 ) % 150 ( ) g m 100 40 TION T ( A E L 50 PU 30 OFFS 0 PO g F O RO –50 T E 20 Z EN C –100 PER –150 10
1 1 0
–200
014 08167-
0 –250
08167-
–3 –2 –1 0 1 –40 –20 0 20 40 60 80 100 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg /°C) TEMPERATURE (°C)
Figure 11. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V Figure 14. Y-Axis Zero g Offset vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V
60 250 200 50 ) % 150 ( ) g m 100 40 TION A T ( L E 50 PU 30 OFFS 0 PO g F O T RO –50 E 20 Z EN C –100 PER –150 10
012
–200
015 08167-
0 –250
08167-
–3 –2 –1 0 1 –40 –20 0 20 40 60 80 100 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg /°C) TEMPERATURE (°C)
Figure 12. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V Figure 15. Z-Axis Zero g Offset vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V Rev. C | Page 8 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE PACKAGE INFORMATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING POWER SAVINGS Power Modes Autosleep Mode Standby Mode SERIAL COMMUNICATIONS SPI Preventing Bus Traffic Errors I2C INTERRUPTS DATA_READY Bit SINGLE_TAP Bit DOUBLE_TAP Bit Activity Bit Inactivity Bit FREE_FALL Bit Watermark Bit Overrun Bit Orientation Bit FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO SELF-TEST REGISTER MAP REGISTER DEFINITIONS Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Improved Tap Bit Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Register 0x3A—TAP_SIGN (Read Only) xSIGN Bits xTAP Bits Register 0x3B—ORIENT_CONF (Read/Write) INT_ORIENT Bit Dead Zone Bits INT_3D Bit Divisor Bits Register 0x3C—Orient (Read Only) Vx Bits xD_ORIENT Bits APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING MECHANICAL CONSIDERATIONS FOR MOUNTING TAP DETECTION IMPROVED TAP DETECTION TAP SIGN THRESHOLD LINK MODE SLEEP MODE VS. LOW POWER MODE OFFSET CALIBRATION USING SELF-TEST ORIENTATION SENSING DATA FORMATTING OF UPPER DATA RATES NOISE PERFORMANCE OPERATION AT VOLTAGES OTHER THAN 2.6 V OFFSET PERFORMANCE AT LOWEST DATA RATES AXES OF ACCELERATION SENSITIVITY LAYOUT AND DESIGN RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE