Datasheet ADXL343 (Analog Devices) - 7

ADXL343 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADXL343 TOP VIEW (Not to Scale) SCL/SCLK V 1 14 13 SDA/SDI/SDIO DD I/O GND 2 12 SDO/ALT ADDRESS RESERVED 3 11 RESERVED +x GND 4 10 NC +y +z GND 5 9 INT2 V 6 7 8 INT1 S CS
002
NOTES 1. NC = NO INTERNAL CONNECTION.
10627- Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VDD I/O Digital Interface Supply Voltage. 2 GND This pin must be connected to ground. 3 RESERVED Reserved. This pin must be connected to VS or left open. 4 GND This pin must be connected to ground. 5 GND This pin must be connected to ground. 6 VS Supply Voltage. 7 CS Chip Select. 8 INT1 Interrupt 1 Output. 9 INT2 Interrupt 2 Output. 10 NC Not Internally Connected. 11 RESERVED Reserved. This pin must be connected to ground or left open. 12 SDO/ALT ADDRESS Serial Data Output (SPI 4-Wire)/Alternate I2C Address Select (I2C). 13 SDA/SDI/SDIO Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire). 14 SCL/SCLK Serial Communications Clock. SCL is the clock for I2C, and SCLK is the clock for SPI. Rev. 0 | Page 6 of 36 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Data Formatting of Upper Data Rates Noise Performance Operation at Voltages Other Than 2.5 V Offset Performance at Lowest Data Rates Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide