Datasheet LTC4300A-3 (Analog Devices) - 7

LTC4300A-3
operaTion Start-Up
Another key feature of the connection circuitry is that it When the LTC4300A-3 first receives power on its V provides bidirectional buffering, keeping the backplane CC pin, either during power-up or during live insertion, it starts and card capacitances isolated. Because of this isolation, in an undervoltage lockout (UVLO) state, ignoring any the waveforms on the backplane busses look slightly activity on the SDA and SCL pins until V different than the corresponding card bus waveforms, as CC rises above 2.5V. The part also waits for V described here. CC2 to rise above 2V. This ensures that the part does not try to function until it has enough voltage to do so.
Input to Output Offset Voltage
During this time, the 1V precharge circuitry is also ac- When a logic low voltage, VLOW1, is driven on any of tive and forces 1V through 100k nominal resistors to the the LTC4300A-3’s data or clock pins, the LTC4300A-3 SDA and SCL pins. Because the I/O card is being plugged regulates the voltage on the other side of the part (call into a live backplane, the voltage on the backplane SDA it VLOW2) to a slightly higher voltage, as directed by the and SCL busses may be anywhere between 0V and V following equation (typical): CC. Precharging the SCL and SDA pins to 1V minimizes the VLOW2 = VLOW1 + 75mV + (VCC/R) • 70 [Ω] worst-case voltage differential these pins will see at the where R is the bus pull-up resistance in ohms. For ex- moment of connection, therefore minimizing the amount ample, if a device is forcing SDAOUT to 10mV where of disturbance caused by the I/O card. VCC = 3.3V and the pull-up resistor R on SDAIN is 10k, Once the LTC4300A-3 comes out of UVLO, it assumes that then the voltage on SDAIN = 10mV + 75mV + (3.3/10000) SDAIN and SCLIN have been inserted into a live system • 70 = 108mV (typical). See the Typical Performance Char- and that SDAOUT and SCLOUT are being powered up at the acteristics section for curves showing the offset voltage same time as itself. Therefore, it looks for either a stop bit as a function of VCC and R. or bus idle condition on the backplane side to indicate the completion of a data transaction. When either one occurs,
Propagation Delays
the part also verifies that both the SDAOUT and SCLOUT During a rising edge, the rise time on each side is determined voltages are high. When all of these conditions are met, by the combined pull-up current of the LTC4300A-3 boost the input-to-output connection circuitry is activated, joining current and the bus resistor and the equivalent capacitance the SDA and SCL busses on the I/O card with those on on the line. If the pull-up currents are the same, a differ- the backplane, and the rise time accelerators are enabled. ence in rise time occurs which is directly proportional to
Connection Circuitry
the difference in capacitance between the two sides. This effect is displayed in Figure 1 for VCC = VCC2 = 3.3V and Once the connection circuitry is activated, the functionality a 10k pull-up resistor on each side (50pF on one side of the SDAIN and SDAOUT pins is identical. A low forced on and 150pF on the other). Since the output side has less either pin at any time results in both pin voltages being low. capacitance than the input, it rises faster and the effective For proper operation, logic low input voltages should be propagation delay is negative. no higher than 0.4V with respect to the ground pin voltage of the LTC4300A-3. SDAIN and SDAOUT enter a logic high There is a finite propagation delay through the connection state only when all devices on both SDAIN and SDAOUT circuitry for falling waveforms. Figure 2 shows the falling release high. The same is true for SCLIN and SCLOUT. edge waveforms for the same VCC, pull-up resistors and This important feature ensures that clock stretching, clock equivalent capacitance conditions as used in Figure  1. synchronization, arbitration and the acknowledge protocol An external NMOS device pulls down the voltage on always work, regardless of how the devices in the system the side with 150pF capacitance; the LTC4300A-3 pulls are tied to the LTC4300A-3. down the voltage on the opposite side, with a delay of 55ns. This delay is always positive and is a function of 4300a3fa 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts Typical Application