LTC2321-14 Typical applicaTionLow Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop VCC 0.1µF 1k NC7SZ04P5X MASTER_CLOCK V 50Ω CC 1k D PRE CONV NL17SZ74USG Q CLR CONTROL CONV ENABLE LOGIC (FPGA, CPLD, LTC2321-14 DSP, ETC.) CNV SCK 10Ω CLKOUT 10Ω GND CMOS/LVDS SDO1 10Ω SDO2 NC7SZ04P5X (× 3) 232114 TA02 232114fc For more information www.linear.com/LTC2321-14 25 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Typical Application Package Description Revision History Related Parts
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