Datasheet LTC6995-1, LTC6995-2 (Analog Devices) - 7

LTC6995-1/LTC6995-2
Typical perForMance characTerisTics V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted. Output Resistance Typical LTC6995-1 Start-Up with vs Supply Current POL = 1
50 45 40 V+ 5V/DIV 35 OUTPUT SOURCING CURRENT RST ANCE (Ω) 30 5V/DIV RESET RELEASED, 25 OUT 100Hz OUTPUT CLOCK 5V/DIV OUTPUT RESET 20 4ms START-UP 699512 G20 15 OUTPUT SINKING CURRENT V+ = 5V 5ms/DIV OUTPUT RESIST DIVCODE = 15 10 RSET = 499k 5 0 2 3 4 5 6 SUPPLY VOLTAGE (V) 699512 G19
pin FuncTions (DCB/S6) V+ (Pin 1/Pin 5):
Supply Voltage (2.25V to 5.5V). This sup- 50ppm/°C or better temperature coefficient. For lower ac- ply should be kept free from noise and ripple. It should be curacy applications an inexpensive 1% thick film resistor bypassed directly to the GND pin with a 0.1µF capacitor. may be used.
DIV (Pin 2/Pin 4):
Programmable Divider and Polarity Limit the capacitance on the SET pin to less than 10pF Input. An internal A/D converter (referenced to V+) moni- to minimize jitter and ensure stability. Capacitance less tors the DIV pin voltage (VDIV) to determine a 4-bit result than 100pF maintains the stability of the feedback circuit (DIVCODE). VDIV may be generated by a resistor divider regulating the VSET voltage. between V+ and GND. Use 1% resistors to ensure an ac- curate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. RST OUT LTC6995-1/ Limit the capacitance on the DIV pin to less than 100pF LTC6995-2 V+ so that V GND V+ DIV settles quickly. The MSB of DIVCODE (POL) C1 R1 determines the polarity of the OUT pin. 0.1µF SET DIV
SET (Pin 3/Pin 3):
Frequency-Setting Input. The voltage 699512 PF RSET R2 on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) pro- grams the master oscillator frequency. The ISET current
RST or RST (Pin 4/Pin 1):
Output Reset. The reset input range is 1.25µA to 20µA. The output oscillation will stop is used to stop the output oscillator and to clear internal if ISET drops below approximately 500nA. A resistor con- dividers. When reset is released the oscillator starts with nected between SET and GND is the most accurate way to a full half period time interval. The output logic state when set the frequency. For best performance, use a precision reset is determined by the programmed DIVCODE. The metal or thin film resistor of 0.5% or better tolerance and LTC6995-1 has an active high RST input. The LTC6995-2 has an active low RST input. 699512fa For more information www.linear.com/LTC6995-1 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts