AD8314PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSRFIN 18 VPOSENBLAD831427 V_DNTOP VIEWVSET 36 V_UP(Not to Scale) 2 00 FLTR 45 COMM 6- 08 01 Figure 2. RM-8 Pin Configuration RFIN 18 VPOSENBL 2AD83147 V_DNTOP VIEWVSET 35 V_UP(Not to Scale) 3 FLTR 45 COMM 006- 08 01 Figure 3. CP-8-1 Pin Configuration Table 3. Pin Function Descriptions Pin No.MnemonicDescription 1 RFIN RF Input. 2 ENBL Connect Pin to VS for Normal Operation. Connect pin to ground for disable mode. 3 VSET Setpoint Input for Operation in Controller Mode. To operate in detector mode connect VSET to V_UP. 4 FLTR Connection for an External Capacitor to Slow the Response of the Output. Capacitor is connected between FLTR and V_UP. 5 COMM Device Common (Ground) 6 V_UP Logarithmic Output. Output voltage increases with increasing input amplitude. 7 V_DN Inversion of V_UP, Governed by: V_DN = 2.25 V − 2 × VUP. 8 VPOS Positive Supply Voltage (VS), 2.7 V to 5.5 V. Rev. B | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INVERTED OUTPUT APPLICATIONS BASIC CONNECTIONS TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT dBV VS. dBm FILTER CAPACITOR OPERATING IN CONTROLLER MODE POWER-ON AND ENABLE GLITCH INPUT COUPLING OPTIONS INCREASING THE LOGARITHMIC SLOPE IN MEASUREMENT MODE EFFECT OF WAVEFORM TYPE ON INTERCEPT MOBILE HANDSET POWER CONTROL EXAMPLES OPERATION AT 2.7 GHz USING THE LFCSP PACKAGE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE