Datasheet AD9200 (Analog Devices) - 16

AD9200 DIFFERENTIAL INPUT OPERATION
The pipelined architecture of the AD9200 operates on both The AD9200 will accept differential input signals. This function rising and falling edges of the input clock. To minimize duty may be used by shorting REFTS and REFBS and driving them cycle variations the recommended logic family to drive the clock as one leg of the differential signal (the top leg is driven into input is high speed or advanced CMOS (HC/HCT, AC/ACT) AIN). In the configuration below, the AD9200 is accepting a logic. CMOS logic provides both symmetrical voltage threshold 1 V p-p signal. See Figure 29. levels and sufficient rise and fall times to support 20 MSPS operation. The AD9200 is designed to support a conversion rate
AD9200
of 20 MSPS; running the part at slightly faster clock rates may
2V
be possible, although at reduced performance levels. Conversely,
AIN 0.1
m
F 1V AVDD/2
some slight performance improvements might be realized by
REFTF REFTS
clocking the AD9200 at slower clock rates.
0.1
m
F 10
m
F REFBS S1 S2 0.1
m
F VREF REFBF ANALOG t S4 C INPUT 1.0
m
F 0.1
m
F S3 t REFSENSE t CH CL INPUT AVDD/2 MODE CLOCK 25ns
Figure 29. Differential Input
DATA DATA 1 OUTPUT AD876 MODE OF OPERATION
The AD9200 may be dropped into the AD876 socket. This will Figure 31. Timing Diagram allow AD876 users to take advantage of the reduced power The power dissipated by the output buffers is largely propor- consumption realized when running the AD9200 on a 3.0 V tional to the clock frequency; running at reduced clock rates analog supply. provides a reduction in power consumption. Figure 30 shows the pin functions of the AD876 and AD9200. The grounded REFSENSE pin and floating MODE pin effec-
DIGITAL INPUTS AND OUTPUTS
tively put the AD9200 in the external reference mode. The Each of the AD9200 digital control inputs, THREE-STATE external reference input for the AD876 will now be placed on and STBY are reference to analog ground. The clock is also the reference pins of the AD9200. referenced to analog ground. The clamp controls will be grounded by the AD876 socket. The The format of the digital output is straight binary (see Figure AD9200 has a 3 clock cycle delay compared to a 3.5 cycle delay 32). A low power mode feature is provided such that for STBY of the AD876. = HIGH and the clock disabled, the static power of the AD9200 will drop below 5 mW.
4V AIN AD9200 OTR 2V REFTS 4V REFTF 10
m
F 0.1
m
F 2V REFBF 0.1 0.1
m
F
m
F REFBS NC MODE AVDD REFSENSE CLAMP CLAMPIN –FS+1LSB +FS OTR VREF –FS +FS–1LSB 0.1
m
F
Figure 32. Output Data Format Figure 30. AD876 Mode
THREE- STATE t CLOCK INPUT DHZ tDEN
The AD9200 clock input is buffered internally with an inverter
DATA (D0–D9)
powered from the AVDD pin. This feature allows the AD9200
HIGH IMPEDANCE
to accommodate either +5 V or +3.3 V CMOS logic input sig- nal swings with the input threshold for the CLK pin nominally Figure 33. Three-State Timing Diagram at AVDD/2. REV. E –15–