AD7729FUNCTIONAL DESCRIPTIONAD7729BASEBAND CODEC Receive Section4.7k V The receive section consists of I and Q receive channels, each IRxP comprising of a simple switched-capacitor filter followed by a IRxI CHANNEL 15-bit sigma-delta ADC. On-board digital filters, which form 4.7k V IRxN part of the sigma-delta ADCs, also perform critical system-level 100pF100pF filtering. Their amplitude and phase response characteristics provide excellent adjacent channel rejection. The receive sec- tion is also provided with a low power sleep mode to place the 4.7k V QRxP receive section on standby between receive bursts, drawing only Q CHANNELQRx minimal current. QRxN4.7k V Switched Capacitor Input The receive section analog front-end is sampled at 13 MHz by a 100pF100pF switched-capacitor filter. The filter has a zero at 6.5 MHz as REFOUT shown in Figure 8a. The receive channel also contains a digital TO INPUT BIAS low-pass filter (further details are contained in the following CIRCUITRY section) which operates at a clock frequency of 6.5 MHz. Due 0.1 m FREFCAPVOLTAGE to the sampling nature of the digital filter, the passband is re- REFERENCE0.1 m F peated about the operating clock frequency and at multiples of the clock frequency (Figure 8b). Because the first null of the switched-capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dBs Figure 9. Example Circuit for Differential Input (Figure 8c), further simplifying the external antialiasing require- Figure 10 shows the recommended single-ended analog input ments (see Figures 9 and 10). circuit. 0 dBsAD7729FRONT-ENDANALOG FILTERTRANSFER4.7k V IRxPFUNCTIONMHzIRx6.51319.5I CHANNEL100pF a) Switched-Cap Filter Frequency Response IRxN0 dBs4.7k V QRxPQRxQ CHANNELDIGITAL FILTER100pFTRANSFERMHzFUNCTIONQRxN6.51319.5 b) Digital Filter Frequency Response VREFOUTBIASHIGH SPEED0 dBsBUFFERSYSTEM FILTER0.1 m FREFCAPVOLTAGETRANSFERREFERENCEMHzFUNCTION0.1 m F6.51319.5 c) Overall System Response of the Receive Channel Figure 10. Example Circuit for Single-Ended Input Figure 8. The circuitry of Figure 9 implements first-order low-pass filters with a 3 dB point at 338 kHz; these are the only filters that must be implemented external to the baseband section to pre- vent aliasing of the sampled signal. REV. 0 –9–