Datasheet AD7652 (Analog Devices) - 7

AD7652
Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns Internal SCLK Period Minimum t19 25 50 100 200 ns Internal SCLK Period Maximum t19 40 70 140 280 ns Internal SCLK HIGH Minimum t20 12 22 50 100 ns Internal SCLK LOW Minimum t21 7 21 49 99 ns SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns BUSY HIGH Width Maximum t24 2 2.5 3.5 5.75 µs Rev. 0 | Page 6 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE SLAVE SERIAL INTERFACE MICROPROCESSOR INTERFACING APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES LAYOUT EVALUATING THE AD7652’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE