Datasheet AD7938, AD7939 (Analog Devices) - 9

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Data Sheet AD7938/AD7939 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 7 6 5 4 3 2 7 6 5 4 3 2 DD IN IN IN IN IN IN DD IN IN IN IN IN IN PIN 1 W/B V V V V V V V W/B V V V V V V V INDICATOR 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 DB0 1 24 V DB0 1 24 V IN1 IN1 DB1 2 23 V PIN 1 IN0 DB1 2 23 VIN0 DB2 3 AD7938/ 22 VREFIN/VREFOUT DB2 3 22 VREFIN/VREFOUT DB3 4 AD7939 21 AGND AD7938/AD7939 DB4 5 20 CS DB3 4 21 AGND TOP VIEW TOP VIEW DB5 6 (Not to Scale) 19 RD DB4 5 (Not to Scale) 20 CS DB6 7 18 WR DB5 6 19 RD DB7 8 17 CONVST DB6 7 18 WR 9 1 10 1 12 13 14 15 16 DB7 8 17 CONVST E N Y N V 9 10 11 12 13 14 15 16 ND DB9 KI DRI DB10 DB11 E N Y N V DG HBE BUS CL V ND DB9 KI DRI DB10 DB11 DB8/ DG HBE BUS
050
V CL NOTES
03715-
DB8/ 1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF
006
THE PACKAGE. CONNECT THE EPAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS.
03715- Figure 2. LFCSP Pin Configuration Figure 3. TQFP Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 to 8 DB0 to DB7 Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the control and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. When reading from the AD7939, the two LSBs (DB0 and DB1) are always 0 and the LSB of the conversion result is available on DB2. 9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that at VDD but should never exceed VDD by more than 0.3 V. 10 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 11 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 10). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data. 12 to DB9 to Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the 14 DB11 control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. 15 BUSY Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY on the 13th rising edge of CLKIN. See Figure 36. 16 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7938/AD7939 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock. 17 CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track mode to hold mode on the fal ing edge of CONVST and the conversion process is initiated at this point. Following power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power up the device. 18 WR Write Input. Active low logic input used in conjunction with CS to write data to the internal registers. 19 RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. 20 CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to the internal registers. Rev. D | Page 9 of 36 Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AD7938 SPECIFICATIONS AD7939 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY ON-CHIP REGISTERS CONTROL REGISTER SEQUENCER OPERATION Writing to the Control Register to Program the Sequencer SHADOW REGISTER CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION Traditional Multichannel Operation (SEQ = SHDW = 0) Using the Sequencer: Programmable Sequence (SEQ = 0, SHDW = 1) Consecutive Sequence (SEQ = 1, SHDW = 1) REFERENCE Digital Inputs VDRIVE Input PARALLEL INTERFACE Reading Data from the AD7938/AD7939 Writing Data to the AD7938/AD7939 POWER MODES OF OPERATION Normal Mode (PM1 = PM0 = 0) Autoshutdown (PM1 = 0; PM0 = 1) Autostandby (PM1 = 1; PM0 = 0) Full Shutdown Mode (PM1 =1; PM0 = 1) POWER vs. THROUGHPUT RATE MICROPROCESSOR INTERFACING AD7938/AD7939 to ADSP-21xx Interface AD7938/AD7939 to ADSP-21065L Interface AD7938/AD7939 to TMS32020, TMS320C25, and TMS320C5x Interface AD7938/AD7939 to 80C186 Interface APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE EVALUATING AD7938/AD7939 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE