Datasheet AD9289 (Analog Devices)

Quad 8-Bit, 65 MSPS, Serial LVDS 3 V A/D Converter AD9289 FEATURES FUNCTIONAL BLOCK DIAGRAM Four ADCs in one package AVDD DFS PDWN DTP DRVDD DRGND Serial LVDS digital output data rates to 520 Mbps (ANSI-644) AD9289 Data and frame clock outputs VIN+A 8 D1+A SNR = 48 dBc (to Nyquist) SERIAL SHA PIPELINE VIN–A ADC LVDS D1–A Excellent linearity DNL = ±0.2 LSB (typical) VIN+B 8 D1+B SERIAL SHA PIPELINE LVDS INL = ±0.25 LSB (typical) VIN–B ADC D1–B 300 MHz full power analog bandwidth VIN+C 8 D1+C SERIAL SHA PIPELINE Power dissipation = 112 mW/channel at 65 MSPS VIN–C ADC LVDS D1–C 1 Vp-p to 2 Vp-p input voltage range VIN+D 8 D1+D SERIAL 3.0 V supply operation SHA PIPELINE VIN–D ADC LVDS D1–D Power-down mode LOCK Digital test pattern enable for timing alignments VREF SENSE FCO+ 0.5V APPLICATIONS FCO– REFT_A REF Tape drives REFB_A SELECT DCO+ DATA RATE REFT_B Medical imaging MULTIPLIER DCO– REFB_B SHARED_REF AGND LVDSBIAS CML CLK+ CLK–
03682-001 Figure 1.
PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS
The AD9289 is a quad 8-bit, 65 MSPS analog-to-digital conver- 1. Four ADCs are contained in a small, space-saving package. ter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. 2. A data clock out (DCO) is provided, which operates up to The product operates at up to a 65 MSPS conversion rate and is 260 MHz and supports double-data rate operation (DDR). optimized for outstanding dynamic performance where a small 3. The outputs of each ADC are serialized LVDS with data package size is critical. rates up to 520 Mbps (8 bits × 65 MSPS). The ADC requires a single, 3 V power supply and an LVDS- 4. The AD9289 operates from a single 3.0 V power supply. compatible sample rate clock for full performance operation. No external reference or driver components are required for 5. The internal clock duty cycle stabilizer maintains many applications. performance over a wide range of input clock duty cycles. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported. The ADC typically consumes 7 mW when enabled. Fabricated on an advanced CMOS process, the AD9289 is available in a 64-ball mini-BGA package (64-BGA). It is specified over the industrial temperature range of –40°C to +85°C.
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Document Outline FEATURES PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS Power Dissipation and Standby Mode Digital Outputs Timing Pin CML Pin DTP Pin Voltage Reference Internal Reference Connection External Reference Operation Power and Ground Recommendations EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE