Datasheet AD7273, AD7274 (Analog Devices)

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3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT AD7273/AD7274 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput rate: 3 MSPS VDD AGND Specified for VDD of 2.35 V to 3.6 V Power consumption 11.4 mW at 3 MSPS with 3 V supplies 10-/12-BIT Wide input bandwidth SUCCESSIVE VIN T/H APPROXIMATION 70 dB SNR at 1 MHz input frequency ADC Flexible power/serial clock speed management VREF No pipeline delays High speed serial interface SCLK SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Temperature range: −40°C to +125°C CONTROL SDATA LOGIC Power-down mode: 0.1 μA typ CS 8-lead TSOT package AD7273/AD7274 8-lead MSOP package DGND
04973-001 Figure 1.
GENERAL DESCRIPTION Table 1.
The AD7273/AD7274 are 10-/12-bit, high speed, low power, successive approximation ADCs, respectively. The parts operate
Part Number Resolution Package
from a single 2.35 V to 3.6 V power supply and feature AD72731 10 8-lead MSOP 8-Lead TSOT throughput rates of up to 3 MSPS. Each part contains a low AD72741 12 8-lead MSOP 8-Lead TSOT noise, wide bandwidth track-and-hold amplifier that can handle AD7276 12 8-lead MSOP 6-Lead TSOT input frequencies in excess of 55 MHz. AD7277 10 8-lead MSOP 6-Lead TSOT AD7278 8 8-lead MSOP 6-Lead TSOT The conversion process and data acquisition are controlled 1 using CS and the serial clock, allowing the devices to interface Parts contain external reference pin. with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this
PRODUCT HIGHLIGHTS
point. The conversion rate is determined by the SCLK. There 1. 3 MSPS ADCs in an 8-lead TSOT package. are no pipeline delays associated with these parts. 2. High throughput with low power consumption. The AD7273/AD7274 use advanced design techniques to achieve very low power dissipation at high throughput rates. 3. Flexible power/serial clock speed management. Allows maximum power efficiency at low throughput rates. The reference for the parts is applied externally and can be in the range of 1.4 V to VDD. This allows the widest dynamic input 4. Reference can be driven up to the power supply. range to the ADC. 5. No pipeline delay. 6. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.
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Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AD7274 SPECIFICATIONS AD7273 SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7273/AD7274 to ADSP-BF53x APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7273/AD7274 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE