Datasheet AD9446 (Analog Devices) - 8

AD9446 TIMING DIAGRAMS N – 1 N A N + 1 IN tCLKL tCLKH 1/fS CLK+ CLK– tPD N – 13 N – 12 N N + 1 DATA OUT 13 CLOCK CYCLES DCO+ DCO–
05490-002
tCPD
Figure 2. LVDS Mode Timing Diagram
N N – 1 N + 1 VIN N + 2 tCLKL tCLKH CLK– CLK+ tPD 13 CLOCK CYCLES DX N – 13 N – 12 N – 1 N DCO+ DCO–
05490-003 Figure 3. CMOS Timing Diagram Rev. 0 | Page 7 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TERMINOLOGY PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE