Datasheet AD7641 (Analog Devices) - 6

link to page 21 link to page 22 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 22 link to page 23 link to page 6 link to page 24 link to page 24 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 7 link to page 26 link to page 26 link to page 21 link to page 22 link to page 7
AD7641 TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 29 and Figure 30) Convert Pulse Width t1 15 701 ns Time Between Conversions (Warp Mode2/Normal Mode3) t2 500/667 ns CNVST Low to BUSY High Delay t3 23 ns BUSY High All Modes (Except Master Serial Read After Convert) t4 385/520 ns Aperture Delay t5 1 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode) t7 385/520 ns Acquisition Time (Warp Mode/Normal Mode) t8 115 ns RESET Pulse Width t9 15 ns RESET Low to BUSY High Delay4 t38 10 ns BUSY High Time from RESET Low4 t39 600 ns PARALLEL INTERFACE MODES (Refer to Figure 31 to Figure 34 ) CNVST Low to Data Valid Delay (Warp Mode/Normal Mode) t10 385/520 ns Data Valid to BUSY Low Delay t11 2 ns Bus Access Request to Data Valid t12 20 ns Bus Relinquish Time t13 2 15 ns MASTER SERIAL INTERFACE MODES5 (Refer to Figure 35 and Figure 36) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SCLK Valid Delay5 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay (Warp Mode/Normal Mode) t17 14/137 ns SYNC Asserted to SCLK First Edge Delay t18 0.5 ns Internal SCLK Period6 t19 8 14 ns Internal SCLK High6 t20 2 ns Internal SCLK Low6 t21 3 ns SDOUT Valid Setup Time6 t22 1 ns SDOUT Valid Hold Time6 t23 0 ns SCLK Last Edge to SYNC Delay6 t24 0 ns CS High to SYNC HI-Z t25 10 ns CS High to Internal SCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns BUSY High in Master Serial Read After Convert6 t28 See Table 4 ns CNVST Low to SYNC Asserted Delay (All Modes) t29 383/500 ns SYNC Deasserted to BUSY Low Delay t30 13 ns SLAVE SERIAL INTERFACE MODES (Refer to Figure 38 and Figure 39) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 1 8 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 12.5 ns External SCLK High t36 5 ns External SCLK Low t37 5 ns 1 See the Conversion Control section. 2 All timings for wideband warp mode are the same as warp mode. 3 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 4 See the Digital Interface section and the RESET section. 5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. Rev. 0 | Page 5 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPPLICATIONS INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS MULTIPLEXED INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) External 2.5 V Reference (PDBUF = High, PDREF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7641 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE