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Datasheet AD7366-5, AD7367-5 (Analog Devices) - 10

ПроизводительAnalog Devices
ОписаниеTrue Bipolar Input, 14-Bit, 2-Channel, Simultaneous Sampling SAR ADC
Страниц / Страница28 / 10 — AD7366-5/AD7367-5. Pin No. Mnemonic. Description
ВерсияB
Формат / Размер файлаPDF / 460 Кб
Язык документаанглийский

AD7366-5/AD7367-5. Pin No. Mnemonic. Description

AD7366-5/AD7367-5 Pin No Mnemonic Description

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ANALOG DEVICES AD7367BRUZ-5Analogue to Digital Converter, SAR Dual, 14 bit, 1 MSPS, 2.7 V, 16.5 V, TSSOP
AD7367BRUZ-5
Analog Devices
378 ₽
EIS Components
Весь мир
AD7367BRUZ-5
Analog Devices
448 ₽
Зенер
Россия и страны ТС
AD7367BRUZ-5
Analog Devices
от 1 690 ₽
T-electron
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AD7367BRUZ5RL7
55 185 ₽

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AD7366-5/AD7367-5 Pin No. Mnemonic Description
18 REFSEL Internal/External Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to decoupling capacitors. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7366-5/ AD7367-5 through the DCAPA and/or DCAPB pins. 19 CS Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output bus is enabled, and the conversion result is output on DOUTA and DOUTB. 20 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366-5/AD7367-5. 21 CNVST Conversion Start, Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes into hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into power- down mode. In this case, the rising edge of CNVST instructs the part to power up again. 22 BUSY Busy Output. BUSY transitions high when a conversion starts and remains high until the conversion completes. 24 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7366-5/AD7367-5. The DGND pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Rev. B | Page 10 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7366-5 SPECIFICATIONS AD7367-5 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUTS TRANSFER FUNCTION Track-and-Hold TYPICAL CONNECTION DIAGRAM DRIVER AMPLIFIER CHOICE VDRIVE REFERENCE MODES OF OPERATION NORMAL MODE SHUTDOWN MODE POWER-UP TIMES SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7366-5/AD7367-5 TO ADSP-218x AD7366-5/AD7367-5 TO ADSP-BF53x AD7366-5/AD7367-5 TO TMS320VC5506 AD7366-5/AD7367-5 TO DSP563xx APPLICATION HINTS LAYOUT AND GROUNDING EVALUATING THE AD7366-5/AD7367-5 OUTLINE DIMENSIONS ORDERING GUIDE
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