Datasheet AD7991, AD7995, AD7999 (Analog Devices) - 3

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AD7991/AD7995/AD7999 SPECIFICATIONS AD79911
The temperature range of the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX.
Table 2. Y Version Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE2, 3 See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz fIN = 1 kHz sine wave for fSCL up to 400 kHz Signal-to-Noise and Distortion (SINAD)4 69.5 70 dB Signal-to-Noise Ratio (SNR)4 70 71 dB Total Harmonic Distortion (THD)4 −75.5 dB Peak Harmonic or Spurious Noise (SFDR)4 −77.5 dB Intermodulation Distortion (IMD)4 fa = 11 kHz, fb = 9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz Second-Order Terms −92 dB Third-Order Terms −88 dB Channel-to-Channel Isolation4 −90 dB fIN = 10 kHz Full-Power Bandwidth4 14 MHz @ 3 dB 1.5 MHz @ 0.1 dB DC ACCURACY2, 5 Resolution 12 Bits Integral Nonlinearity4 ±1 LSB ±0.5 LSB Differential Nonlinearity4 ±0.9 LSB Guaranteed no missed codes to 12 bits ±0.5 LSB Offset Error4 ±1 ±7 LSB Offset Error Matching ±0.5 LSB Offset Temperature Drift 4.43 ppm/°C Gain Error4 ±2 LSB Gain Error Matching ±0.7 LSB Gain Temperature Drift 0.69 ppm/°C ANALOG INPUT Input Voltage Range 0 VREF V VREF = VIN3/VREF or VDD DC Leakage Current ±1 μA Input Capacitance 34 pF Channel 0 to Channel 2—during acquisition phase 4 pF Channel 0 to Channel 2—outside acquisition phase 35 pF Channel 3—during acquisition phase 5 pF Channel 3—outside acquisition phase REFERENCE INPUT VREF Input Voltage Range 1.2 VDD V DC Leakage Current ±1 μA VREF Input Capacitance 5 pF Outside conversion phase 35 pF During conversion phase Input Impedance 69 kΩ Rev. B | Page 3 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7991 AD7995 AD7999 I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER OPERATION ADC Transfer Function TYPICAL CONNECTION DIAGRAM ANALOG INPUT INTERNAL REGISTER STRUCTURE CONFIGURATION REGISTER SAMPLE DELAY AND BIT TRIAL DELAY CONVERSION RESULT REGISTER SERIAL INTERFACE SERIAL BUS ADDRESS WRITING TO THE AD7991/AD7995/AD7999 READING FROM THE AD7991/AD7995/AD7999 PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE MODE OF OPERATION OUTLINE DIMENSIONS ORDERING GUIDE