Datasheet AD9262 (Analog Devices)

16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC AD9262 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD SNR: 83 dB (85 dBFS) to 10 MHz input SFDR: −87 dBc to 10 MHz input ORA VIN+A LOW-PASS SAMPLE D15A Noise figure: 15 dB CT Σ-Δ DC CMOS MODULATOR DECIMATION RATE CORRECT BUFFER VIN–A FILTER CONVERTER Input impedance: 1 kΩ D0A Power: 600 mW GAIN QUADRATURE ADJ ERROR 1.8 V analog supply operation VREF ESTIMATE PHASE AD9262 ADJ CFILT 1.8 V to 3.3 V output supply DCO Selectable bandwidth VIN–B LOW-PASS SAMPLE D15B CT Σ-Δ DC CMOS 2.5 MHz/5 MHz/10 MHz real MODULATOR DECIMATION RATE CORRECT BUFFER VIN+B FILTER CONVERTER D0B 5 MHz/10 MHz/20 MHz complex CLK+ PHASE- SERIAL ORB Output data rate: 30 MSPS to 160 MSPS LOCKED INTERFACE CLK– LOOP Integrated dc and quadrature correction AGND SDIO SCLK CSB DGND
07772-001
Integrated decimation filters
Figure 1
Integrated sample rate converter
The AD9262 incorporates an integrated dc correction and
On-chip PLL clock multiplier
quadrature estimation block that corrects for gain and phase
On-chip voltage reference Offset binary, Gray code, or twos complement data format
mismatch between the two channels. This functional block
Serial control interface (SPI)
proves invaluable in complex signal processing applications such as direct conversion receivers.
APPLICATIONS
The digital output data is presented in offset binary, Gray code,
Baseband quadrature receivers: CDMA2000, W-CDMA,
or twos complement format. A data clock output (DCO) is
multicarrier GSM/EDGE, 802.16x, and LTE
provided to ensure proper timing with the receiving logic. The
Quadrature sampling instrumentation
AD9262 has the added feature of interleaving Channel A and
Medical equipment
Channel B data onto one 16-bit bus, simplifying on-board routing.
Radio detection and ranging (RADAR)
The ADC is available in three different bandwidth options of
GENERAL DESCRIPTION
2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog The AD9262 is a dual channel, 16-bit analog-to-digital conver- supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW. ter (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ) The AD9262 is available in a 64-lead LFCSP and is specified architecture that achieves −87 dBc of dynamic range over a over the industrial temperature range (−40°C to +85°C). 10 MHz input bandwidth. The integrated features and characteris-
PRODUCT HIGHLIGHTS
tics unique to the continuous time Σ-Δ architecture significantly 1. Continuous time Σ-Δ architecture efficiently achieves high simplify its use and minimize the need for external components. dynamic range and wide bandwidth. The AD9262 has a resistive input impedance that relaxes the 2. Passive input structure reduces or eliminates the require- requirements of the driver amplifier. In addition, a 32× oversam- ments for a driver amplifier. pled fifth-order continuous time loop filter significantly attenuates 3. An oversampling ratio of 32× and high order loop filter out-of-band signals and aliases, reducing the need for external provide excellent alias rejection reducing or eliminating the filters at the input. need for antialiasing filters. An external clock input or the integrated integer-N PLL provides 4. An integrated decimation filter, sample rate converter, PLL the 640 MHz internal clock needed for the oversampled conti- clock multiplier, and voltage reference provide ease of use. nuous time Σ-Δ modulator. On-chip decimation filters and sample 5. Integrated dc correction and quadrature error correction. rate converters reduce the modulator data rate from 640 MSPS to a 6. Operates from a single 1.8 V analog power supply and user-defined output data rate between 30 MSPS and 160 MSPS, 1.8 V to 3.3 V output supply. enabling a more efficient and direct interface.
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Digital Outputs Digital Output Format Interleaved Outputs Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide