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Datasheet AD9266 (Analog Devices) - 9

ПроизводительAnalog Devices
Описание16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
Страниц / Страница33 / 9 — AD9266. Data Sheet. TIMING SPECIFICATIONS Table 5. Parameter. Test …
ВерсияB
Формат / Размер файлаPDF / 1.1 Мб
Язык документаанглийский

AD9266. Data Sheet. TIMING SPECIFICATIONS Table 5. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit

AD9266 Data Sheet TIMING SPECIFICATIONS Table 5 Parameter Test Conditions/Comments Min Typ Max Unit

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AD9266 Data Sheet TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output 10 ns relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an input 10 ns relative to the SCLK rising edge Rev. B | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AD9266-65 AD9266-40 AD9266-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
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