Datasheet AD9645 (Analog Devices) - 7

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AD9645 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4. Parameter1, 2 Temp Min Typ Max Unit
CLOCK3 Input Clock Rate Full 10 1000 MHz Conversion Rate4 Full 10 80/125 MSPS Clock Pulse Width High (t ) Full 6.25/4.00 ns EH Clock Pulse Width Low (t ) Full 6.25/4.00 ns EL OUTPUT PARAMETERS3 Propagation Delay (t ) Full 1.5 2.3 3.1 ns PD Rise Time (t ) (20% to 80%) Full 300 ps R Fall Time (t ) (20% to 80%) Full 300 ps F FCO Propagation Delay (t ) Full 1.5 2.3 3.1 ns FCO DCO Propagation Delay (t )5 Full t + (t /16) ns CPD FCO SAMPLE DCO to Data Delay (t )5 Full (t /16) − 300 t /16 (t /16) + 300 ps DATA SAMPLE SAMPLE SAMPLE DCO to FCO Delay (t )5 Full (t /16) − 300 t /16 (t /16) + 300 ps FRAME SAMPLE SAMPLE SAMPLE Lane Delay (t ) 90 ps LD Data-to-Data Skew (t − t ) Full ±50 ±200 ps DATA-MAX DATA-MIN Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)6 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (t ) 25°C 1 ns A Aperture Uncertainty (Jitter, t ) 25°C 174 fs rms J Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output mode. 5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit
SPI TIMING REQUIREMENTS See Figure 68 t Setup time between the data and the rising edge of SCLK 2 ns min DS t Hold time between the data and the rising edge of SCLK 2 ns min DH t Period of the SCLK 40 ns min CLK t Setup time between CSB and SCLK 2 ns min S t Hold time between CSB and SCLK 2 ns min H t SCLK pulse width high 10 ns min HIGH t SCLK pulse width low 10 ns min LOW t Time required for the SDIO pin to switch from an input to an output relative 10 ns min EN_SDIO to the SCLK falling edge (not shown in Figure 68) t Time required for the SDIO pin to switch from an output to an input relative 10 ns min DIS_SDIO to the SCLK rising edge (not shown in Figure 68) Rev. B | Page 6 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9645-80 AD9645-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE