Datasheet AD9250 (Analog Devices) - 10

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AD9250 Data Sheet TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS (See Figure 62) tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CS and SCLK 2 ns tH Hold time between CS and SCLK 2 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an 10 ns output relative to the SCLK falling edge (not shown in figures) tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the SCLK rising edge (not shown in figures) tSPI_RST Time required after hard or soft reset until SPI access is available 500 µs (not shown in figures)
Timing Diagrams N – 36 SAMPLE N N + 1 N – 35 ANALOG N – 34 N – 1 INPUT N – 33 SIGNAL CLK– CLK+ CLK– CLK+ SERDOUT1± SERDOUT0± SAMPLE N – 36 SAMPLE N – 35 SAMPLE N – 34
002
ENCODED INTO 2 ENCODED INTO 2 ENCODED INTO 2 8b/10b SYMBOLS 8b/10b SYMBOLS 8b/10b SYMBOLS
10559- Figure 2. Data Output Timing
RFCLK CLK+ CLK– tREFS tREFSRF tREFH tREFHRF SYSREF+ SYSREF+ SYSREF– SYSREF–
003
NOTES 1. CLOCK INPUT IS EITHER RFCLK OR CLK±, NOT BOTH.
10559- Figure 3. SYSREF± Setup and Hold Timing Rev. E | Page 10 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide