Datasheet AD7175-8 (Analog Devices) - 6

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Data Sheet AD7175-8 Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS Input High Voltage, V 1 2 V ≤ IOVDD < 2.3 V 0.65 × V INH IOVDD 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 × IOVDD V Input Low Voltage, V 1 2 V ≤ IOVDD < 2.3 V 0.35 × IOVDD V INL 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 V Hysteresis1 IOVDD ≥ 2.7 V 0.08 0.25 V IOVDD < 2.7 V 0.04 0.2 V Leakage Current −10 +10 µA LOGIC OUTPUT (DOUT/RDY) Output High Voltage, V 1 IOVDD ≥ 4.5 V, I = 1 mA 0.8 × IOVDD V OH SOURCE 2.7 V ≤ IOVDD < 4.5 V, I = 500 µA 0.8 × IOVDD V SOURCE IOVDD < 2.7 V, I = 200 µA 0.8 × IOVDD V SOURCE Output Low Voltage, V 1 IOVDD ≥ 4.5 V, I = 2 mA 0.4 V OL SINK 2.7 V ≤ IOVDD < 4.5 V, I = 1 mA 0.4 V SINK IOVDD < 2.7 V, I = 400 µA 0.4 V SINK Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF SYSTEM CALIBRATION1 Full-Scale (FS) Calibration Limit 1.05 × FS V Zero-Scale Calibration Limit −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V POWER REQUIREMENTS Power Supply Voltage AVDD1 to AVSS 4.5 5 5.5 V AVDD2 to AVSS4 2 2.5 to 5 5.5 V AVSS to DGND −2.75 0 V IOVDD to DGND4 2 2.5 to 5 5.5 V IOVDD to AVSS For AVSS < DGND 6.35 V POWER SUPPLY CURRENTS5 All outputs unloaded, digital inputs connected to IOVDD or DGND Full Operating Mode AVDD1 Current Analog input and reference input buffers 1.4 1.65 mA (AIN±, REF±) disabled, external reference Analog input and reference input buffers 1.75 2 mA disabled, internal reference Analog input and reference input buffers 13 16 mA enabled, external reference Each buffer: AIN+, AIN−, REF+, REF− 2.9 mA AVDD2 Current External reference 4.5 5 mA Internal reference 4.75 5.2 mA IOVDD Current External clock 2.5 2.8 mA Internal clock 2.75 3.1 mA External crystal 3 mA Standby Mode (LDO On) Internal reference off, total current 30 µA consumption Internal reference on, total current 425 µA consumption Power-Down Mode Full power-down (including LDO and 5 10 µA internal reference) Rev. 0 | Page 5 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7175-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7175-8 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH POWER-DOWN SWITCH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE