Datasheet AD9655 (Analog Devices) - 5

AD9655 Data Sheet
AVDD = 1.8 V, DRVDD = 1.8 V, 2.8 V p-p full-scale differential input mode, VREF = 1.4 V, AIN = −1.0 dBFS, 125 MSPS, unless otherwise noted.
Table 2. Parameter1 Temperature Min Typ Max Unit
RESOLUTION 16 Bits ACCURACY No Missing Codes Full Guaranteed2 Offset Error Full −0.12 +0.2 +0.48 % FSR Offset Matching Full −0.2 +0.1 +0.33 % FSR Gain Error Full −2.4 +2.8 +8.2 % FSR Gain Matching Full −1.2 +0.4 +1.9 % FSR Differential Nonlinearity (DNL) Full −0.99 +1.43 LSB 25°C ±0.7 LSB Integral Nonlinearity (INL) Full −8.5 +8.5 LSB 25°C ±3.4 LSB TEMPERATURE DRIFT Gain Error Full −66 ppm/°C Offset Error Full 0.9 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1.4 V Mode) Full 1.37 1.38 1.41 V Load Regulation at 1.0 mA (VREF = 1.4 V) 25°C 186 mV Input Resistance 25°C 7.5 kΩ INPUT-REFERRED NOISE VREF = 1.4 V 25°C 2 LSB rms ANALOG INPUTS Differential Input Voltage (VREF = 1.4 V) Full 2.8 V p-p Common-Mode Voltage Full 0.9 V Common-Mode Range 25°C 0.7 1.0 V Differential Input Resistance 25°C 1.9 kΩ Differential Input Capacitance 25°C 6.6 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V I 3 AVDD Full 101 111 mA IDRVDD (ANSI-644 Mode)3 Full 73 79 mA IDRVDD (Reduced Range Mode)3 Full 62 68 mA TOTAL POWER CONSUMPTION Sine Wave Input (Two Channels, Including Output Drivers ANSI-644 Mode) Full 313 342 mW Sine Wave Input (Two Channels, Including Output Drivers Reduced Range Mode) Full 293 322 mW Power-Down Full 2 4 mW Standby4 Full 155 172 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 No missing codes guaranteed if Register 0x18 = 0x04 (default, no digital scaling of the output). 3 Measured with a low input frequency, −1 dBFS sine wave on both channels, DDR operation, and two-lane operation. 4 Standby mode can be control ed via the SPI. Rev. 0 | Page 4 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.4 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—0 Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—000 Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—Disable SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—000 Clock Monitor Control (Register 0x112) Bit 7—Open Bit 6—0 (Reserved) Bits[5:3]—Recovery Mode Bits[2:0]— Recovery Mode Setup VREF Control (Register 0x114) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE BYPASSING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE