Datasheet ATmega16, ATmega16L (Complete) (Atmel) - 9

ATmega16(L)
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector posi- tion. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F.
ALU
–
Arithmetic
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
Logic Unit
working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
Status Register
The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
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2466T–AVR–07/10 Document Outline Features Pin Configurations Disclaimer Overview Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF Resources Data Retention About Code Examples AVR CPU Core Introduction Architectural Overview ALU – Arithmetic Logic Unit Status Register General Purpose Register File The X-register, Y- register and Z-register Stack Pointer Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR ATmega16 Memories In-System Reprogrammable Flash Program Memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register – EEARH and EEARL The EEPROM Data Register – EEDR The EEPROM Control Register – EECR EEPROM Write During Power-down Sleep Mode Preventing EEPROM Corruption I/O Memory System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH Asynchronous Timer Clock – clkASY ADC Clock – clkADC Clock Sources Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator External RC Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock Timer/Counter Oscillator Power Management and Sleep Modes MCU Control Register – MCUCR Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode Standby Mode Extended Standby Mode Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins JTAG Interface and On-chip Debug System System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Control and Status Register – MCUCSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer Watchdog Timer Control Register – WDTCR Interrupts Interrupt Vectors in ATmega16 Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR I/O Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected pins Alternate Port Functions Special Function I/O Register – SFIOR Alternate Functions of Port A Alternate Functions of Port B Alternate Functions of Port C Alternate Functions of Port D Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND External Interrupts MCU Control Register – MCUCR MCU Control and Status Register – MCUCSR General Interrupt Control Register – GICR General Interrupt Flag Register – GIFR 8-bit Timer/Counter0 with PWM Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source Special Function IO Register – SFIOR 16-bit Timer/Counter1 Overview Registers Definitions Compatibility Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Pin Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask Register – TIMSK(1) Timer/Counter Interrupt Flag Register – TIFR 8-bit Timer/Counter2 with PWM and Asynchronous Operation Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Timer/Counter Register – TCNT2 Output Compare Register – OCR2 Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter2 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter Prescaler Special Function IO Register – SFIOR Serial Peripheral Interface – SPI SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR Data Modes USART Overview AVR USART vs. AVR UART – Compatibility Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2X) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Sending Frames with 5 to 8 Data Bit Sending Frames with 9 Data Bit Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Databits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Multi-processor Communication Mode Using MPCM Accessing UBRRH/ UCSRC Registers Write Access Read Access USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA USART Control and Status Register B – UCSRB USART Control and Status Register C – UCSRC USART Baud Rate Registers – UBRRL and UBRRH Examples of Baud Rate Setting Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology Electrical Interconnection Data Transfer and Frame Format Transferring Bits START and STOP Conditions Address Packet Format Data Packet Format Combining Address and Data Packets into a Transmission Multi-master Bus Systems, Arbitration and Synchronization Overview of the TWI Module SCL and SDA Pins Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit TWI Register Description TWI Bit Rate Register – TWBR TWI Control Register – TWCR TWI Status Register – TWSR TWI Data Register – TWDR TWI (Slave) Address Register – TWAR Using the TWI Transmission Modes Master Transmitter Mode Master Receiver Mode Slave Receiver Mode Slave Transmitter Mode Miscellaneous States Combining Several TWI Modes Multi-master Systems and Arbitration Analog Comparator Special Function IO Register – SFIOR Analog Comparator Control and Status Register – ACSR Analog Comparator Multiplexed Input Analog to Digital Converter Features Operation Starting a Conversion Prescaling and Conversion Timing Differential Gain Channels Changing Channel or Reference Selection ADC Input Channels ADC Voltage Reference ADC Noise Canceler Analog Input Circuitry Analog Noise Canceling Techniques Offset Compensation Schemes ADC Accuracy Definitions ADC Conversion Result ADC Multiplexer Selection Register – ADMUX ADC Control and Status Register A – ADCSRA The ADC Data Register – ADCL and ADCH Special FunctionIO Register – SFIOR JTAG Interface and On-chip Debug System Features Overview Test Access Port – TAP TAP Controller Using the Boundary-scan Chain Using the On-chip Debug System On-chip Debug Specific JTAG Instructions PRIVATE0; $8 PRIVATE1; $9 PRIVATE2; $A PRIVATE3; $B On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR Using the JTAG Programming Capabilities Bibliography IEEE 1149.1 (JTAG) Boundary-scan Features System Overview Data Registers Bypass Register Device Identification Register Reset Register Boundary-scan Chain Boundary-scan Specific JTAG Instructions EXTEST; $0 IDCODE; $1 SAMPLE_PRELOAD; $2 AVR_RESET; $C BYPASS; $F Boundary-scan Related Register in I/O Memory MCU Control and Status Register – MCUCSR Boundary-scan Chain Scanning the Digital Port Pins Boundary-scan and the Two-wire Interface Scanning the RESET Pin Scanning the Clock Pins Scanning the Analog Comparator Scanning the ADC ATmega16 Boundary-scan Order Boundary-scan Description Language Files Boot Loader Support – Read- While-Write Self- Programming Features Application and Boot Loader Flash Sections Application Section BLS – Boot Loader Section Read-While-Write and no Read- While-Write Flash Sections RWW – Read-While- Write Section NRWW – No Read- While-Write Section Boot Loader Lock Bits Entering the Boot Loader Program Store Program Memory Control Register – SPMCR Addressing the Flash during Self- Programming Self-Programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) Performing a Page Write Using the SPM Interrupt Consideration while Updating BLS Prevent Reading the RWW Section during Self-Programming Setting the Boot Loader Lock Bits by SPM EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock Bits from Software Preventing Flash Corruption Programming Time for Flash when using SPM Simple Assembly Code Example for a Boot Loader ATmega16 Boot Loader Parameters Memory Programming Program And Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Page Size Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading SPI Serial Programming Pin Mapping SPI Serial Programming Algorithm Data Polling Flash Data Polling EEPROM Serial Programming Instruction set SPI Serial Programming Characteristics Programming via the JTAG Interface Programming Specific JTAG Instructions AVR_RESET ($C) PROG_ENABLE ($4) PROG_COMMANDS ($5) PROG_PAGELOAD ($6) PROG_PAGEREAD ($7) Data Registers Reset Register Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register Programming Algorithm Entering Programming Mode Leaving Programming Mode Performing Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuses Programming the Lock Bits Reading the Fuses and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive Two-wire Serial Interface Characteristics SPI Timing Characteristics ADC Characteristics ATmega16 Typical Characteristics Active Supply Current Idle Supply Current Power-Down Supply Current Power-Save Supply Current Standby Supply Current Pin Pullup Pin Driver Strength Pin Thresholds And Hysteresis Bod Thresholds And Analog Comparator Offset Internal Oscillator Speed Current Consumption Of Peripheral Units Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 40P6 44M1 Errata ATmega16(L) Rev. M ATmega16(L) Rev. L ATmega16(L) Rev. K ATmega16(L) Rev. J ATmega16(L) Rev. I ATmega16(L) Rev. H Datasheet Revision History Rev. 2466T-07/10 Rev. 2466S-05/09 Rev. 2466R-06/08 Rev. 2466Q-05/08 Rev. 2466P-08/07 Rev. 2466O-03/07 Rev. 2466N-10/06 Rev. 2466M-04/06 Rev. 2466L-06/05 Rev. 2466K-04/05 Rev. 2466J-10/04 Rev. 2466I-10/04 Rev. 2466H-12/03 Rev. 2466G-10/03 Rev. 2466F-02/03 Rev. 2466E-10/02 Rev. 2466D-09/02 Rev. 2466C-03/02 Table of Contents