Datasheet LTC3770 (Analog Devices) - 8

LTC3770
PIN FUNCTIONS (UH Package/G Package)
sets the ramp rate for the output voltage. When the IC is
BG (Pin 21/Pin 22):
Bottom Gate Driver Output. This pin confi gured to be the slave of two outputs, the VFB voltage drives the gate of the bottom N-channel MOSFET between of the master IC is reproduced by a resistor divider and ground and INTVCC. applied to this pin. An internal 1.4μA soft-start current is
PGND (Pin 22/Pin 23):
Power Ground. Connect this pin charging this pin during the soft-start phase. closely to the source of the bottom N-channel MOSFET,
PLLFLTR (Pin 12/Pin 15):
The Phase-Locked Loop’s the (–) terminal of CVCC and the (–) terminal of CIN. Lowpass Filter is Tied to This Pin. The voltage at this pin
SENSE– (Pin 23) UH Package:
Current Sense Comparator defaults to 1.18V when the IC is not synchronized with Input. The (–) input to the current comparator is used an external clock at the PLLIN pin. to accurately Kelvin sense the bottom side of the sense
PLLIN (Pin 13/Pin 16):
External Synchronization Input to resistor or MOSFET. This pin is co-bonded with PGND Phase Detector. This pin is internally terminated to SGND internally in the SSOP package. with a 50k resistor.
SENSE+ (Pin 24) UH Package:
Current Sense Comparator
VIN (Pin 14/Pin 17):
Main Input Supply. Decouple this pin Input. The (+) input to the current comparator is normally to PGND with a capacitor (0.1μF to 1μF). connected to the SW node unless using a sense resistor. This pin is co-bonded with SW internally in the SSOP
VINSNS (Pin 15) UH Package:
VIN Voltage Sense Input. package. Normally this pin is tied to VIN. However, in certain applications when the IC is powered from a separate
SW (Pin 25/Pin 24):
Switch Node. The (–) terminal of the supply, VINSNS is tied to the upper MOSFET supply to boot-strap capacitor CB connects here. This pin swings sense the VIN voltage. The pin is co-bonded with VIN in from a diode voltage drop below ground up to VIN. the SSOP package.
TG (Pin 26/Pin 25):
Top Gate Drive Output. This pin drives
ZVIN (Pin 16/Pin 18):
Post-Package Zener-Trim Voltage the top N-channel MOSFET with a voltage swing equal to Input. Under normal conditions this pin should always be INTVCC, superimposed on the switch node voltage SW. connected to INTVCC.
BOOST (Pin 27/Pin 26):
Boosted Floating Driver Supply.
Z1 (Pin 17/Pin 19):
Post-Package Zener-Trim Control. The (+) terminal of the boot-strap capacitor CB connects This pin is a multifunctional pin used in production for here. This pin swings from a diode voltage drop below post-package trimming and tracking. Ground this pin under INTVCC up to VIN + INTVCC. normal soft-start operation. Connecting this pin to INTVCC
Z0 (Pin 28/Pin 27):
Dead Time Control Input. Applying a will turn off the soft-start current during tracking. DC voltage will vary the dead time between TG-Low and
Z2 (Pin 18/Pin 20):
Post-Package Zener-Trim Control. BG-High transition. Do not force a voltage higher than This pin is used in production for Post-Package trimming. 5V on this pin. Ground this pin or tie to INTVCC under normal operation.
FCB (Pin 29/Pin 28):
Forced Continuous Input. Connect
INTVCC (Pin 19/Pin 21):
Internal 5V Regulator Output. The this pin to SGND to forced continuous synchronization control circuits are powered from this voltage. Decouple this operation at low load, to INTVCC to enable discontinuous pin to PGND with a minimum of 4.7μF low ESR tantalum mode operation at low load or to a resistive divider from or ceramic capacitor. a secondary output when using a secondary winding.
DRVCC (Pin 20) UH Package Gate:
Driver Voltage Input.
RUN (Pin 30/Pin 1):
Run Control Input. A voltage above Must be connected to INTVCC externally. Do not exceed 1.5V turns on the IC. Forcing this pin below 1.5V shuts 7V at this pin. This pin is co-bonded to INTVCC internally down the device. in the SSOP package. 3770fc 8