Datasheet LTC2301, LTC2305 (Analog Devices) - 4

LTC2301/LTC2305
DYNAMIC ACCURACY The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C and AIN = –1dBFS. (Notes 4,9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 1kHz l 71 73.4 dB SNR Signal-to-Noise Ratio fIN = 1kHz l 71 73.5 dB THD Total Harmonic Distortion fIN = 1kHz l –91 –77 dB SFDR Spurious Free Dynamic Range fIN = 1kHz, First 5 Harmonics l 79 92 dB Channel-to-Channel Isolation fIN = 1kHz –109 dB Full Linear Bandwidth fIN = 1kHz 700 kHz –3dB Input Linear Bandwidth (Note 10) 25 MHz Aperture Delay 13 ns Transient Response Full-Scale Step 240 ns
INTERNAL REFERENCE CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Notes 4) PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 l 2.46 2.50 2.54 V VREF Output Tempco IOUT = 0 ±25 ppm/°C VREF Output Impedance –0.1mA ≤ IOUT ≤ 0.1mA 8 kΩ VREFCOMP Output Voltage IOUT = 0 4.096 V VREF Line Regulation VDD = 4.75V to 5.25V 0.8 mV/V
I2C INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Notes 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l 2.85 V VIL Low Level Input Voltage l 1.5 V VIHA High Level Input Voltage for Address Pins A1, A0 l 4.75 V VILA Low Level Input Voltage for Address Pins A1, A0 l 0.25 V RINH Resistance from A1, A0 to VDD to Set Chip l 10 kΩ Address Bit to 1 RINL Resistance from A1, A0 to GND to Set Chip l 10 kΩ Address Bit to 0 RINF Resistance from A1, A0 to GND or VDD to Set l 2 MΩ Chip Address Bit to Float II Digital Input Current VIN = VDD l –10 10 μA VHYS Hysteresis of Schmitt Trigger Inputs (Note 8) l 0.25 V VOL Low Level Output Voltage (SDA) I = 3mA l 0.4 V tOF Output Fall Time VIN(MIN) to VIL(MAX) Bus Load CB 10pF to 400pF (Note 11) l 20 + 0.1CB 250 ns tSP Input Spike Suppression l 50 ns CCAX External Capacitance Load on Chip Address Pins l 10 pF (A1, A0) for Valid Float 23015fb 4