LTC2207/LTC2206 16-Bit, 105Msps/80Msps ADCs FEATURESDESCRIPTION ■ Sample Rate: 105Msps/80Msps The LTC®2207/LTC2206 are 105Msps/80Msps, sampling ■ 78.2dBFS Noise Floor 16-bit A/D converters designed for digitizing high fre- ■ 100dB SFDR quency, wide dynamic range signals up to input frequencies ■ SFDR >82dB at 250MHz (1.5VP-P Input Range) of 700MHz. The input range of the ADC can be optimized ■ PGA Front End (2.25VP-P or 1.5VP-P Input Range) with the PGA front end. ■ 700MHz Full Power Bandwidth S/H ■ The LTC2207/LTC2206 are perfect for demanding com- Optional Internal Dither ■ munications applications, with AC performance that Optional Data Output Randomizer ■ includes 78.2dB Noise Floor and 100dB spurious free Single 3.3V Supply ■ dynamic range (SFDR). Ultralow jitter of 80fsRMS allows Power Dissipation: 900mW/725mW ■ undersampling of high input frequencies with excellent Optional Clock Duty Cycle Stabilizer ■ noise performance. Maximum DC specs include ±4LSB Out-of-Range Indicator ■ INL, ±1LSB DNL (no missing codes) over temperature. Pin-Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) A separate output power supply allows the CMOS output 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) swing to range from 0.5V to 3.6V. 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) The ENC+ and ENC– inputs may be driven differentially 40Msps: LTC2204 (16-Bit) or single-ended with a sine wave, PECL, LVDS, TTL or 25Msps: LTC2203 (16-Bit) Single-Ended Clock CMOS inputs. An optional clock duty cycle stabilizer al- 10Msps: LTC2202 (16-Bit) Single-Ended Clock lows high performance at full speed with a wide range of ■ 48-Pin 7mm × 7mm QFN Package clock duty cycles. APPLICATIONS L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ Telecommunications ■ Receivers ■ Cellular Base Stations ■ Spectrum Analysis ■ Imaging Systems ■ ATE TYPICAL APPLICATIONLTC2207: 64K Point FFT, 3.3V f SENSE IN = 14.8MHz, –1dBFS, OV PGA = 0, 105Msps DD 0.5V TO 3.6V 1.25V INTERNAL ADC VCM 0 COMMON MODE REFERENCE 0.1μF –10 2.2μF BIAS VOLTAGE GENERATOR –20 OF –30 CLKOUT+ AIN+ –40 + CLKOUT– 16-BIT CORRECTION OUTPUT –50 ANALOG S/H D15 PIPELINED LOGIC AND DRIVERS –60 INPUT AMP • ADC CORE SHIFT REGISTER – • –70 AIN– • –80 D0 AMPLITUDE (dBFS) –90 OGND –100 CLOCK/DUTY CYCLE V 3.3V DD –110 CONTROL 0.1μF 0.1μF 0.1μF –120 GND –130 22076 TA01 0 10 20 30 40 50 ENC+ ENC– PGA SHDN DITH MODE OE RAND FREQUENCY (MHz) ADC CONTROL INPUTS 22076 G05 22076fc 1
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