LTC1401 W UTI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range,unless otherwise noted specifications are at TA = 25 ° C. VCC = 3V, fSAMPLE = 200kHz, tr = tf = 5ns, unless otherwise specified.SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS fSAMPLE(MAX) Maximum Sampling Frequency ● 200 kHz tCONV Conversion Time fCLK = 3.2MHz ● 4.1 µs tACQ Acquisition Time 315 ns fCLK CLK Frequency ● 0.1 3.2 MHz tCLK CLK Pulse Width (Notes 5 and 8) ● 60 ns tWK(NAP) Time to Wake Up from Nap Mode 350 ns t1 CLK Pulse Width to Return to Active Mode ● 60 ns t2 CONV↑ to CLK↑ Setup Time ● 100 ns t3 CONV↑ After Leading CLK↑ ● 0 ns t4 CONV Pulse Width (Note 7) ● 50 ns t5 Time from CLK↑ to Sample Mode 80 ns t6 Aperture Delay of Sample-and-Hold Jitter < 50ps 45 ns t7 Minimum Delay Between Conversion (Note 5) ● 350 550 ns t8 Delay Time, CLK↑ to DOUT Valid CLOAD = 20pF ● 60 120 ns t9 Delay Time, CLK↑ to DOUT Hi-Z CLOAD = 20pF ● 60 120 ns t10 Time from Previous Data Remains Valid After CLK↑ CLOAD = 20pF ● 15 50 ns t11 Minimum Time Between Nap/Sleep Request to Wake Up Request (Notes 5 and 8) ● 50 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute Note 6: Integral nonlinearity is defined as the deviation of a code from a Maximum Rating condition for extended periods may affect device straight line passing through the actual endpoints of the transfer curve. reliability and lifetime. The deviation is measured from the center of the quantization band. Note 2: All voltage values are with respect to GND. Note 7: The rising edge of CONV starts a conversion. If CONV returns low Note 3: When these pin voltages are taken below GND or above VCC, they at a bit decision point during the conversion, it can create small errors. For will be clamped by internal diodes. This product can handle input currents best performance, ensure that CONV returns low either within 120ns after greater than 40mA without latch-up if the pin is driven below GND or the conversion starts (i.e., before the first bit decision) or after the 14 above VCC. clock cycles. (Figure 13 Timing Diagram). Note 4: When these pin voltages are taken below GND, they will be clamped Note 8: If this timing specification is not met, the device may not respond by internal diodes. This product can handle input currents greater than 40mA to a request for a conversion. To recover from this condition a NAP without latch-up if the pin is driven below GND. These pins are not clamped request is required. to VCC. 1401fa 4
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