LTC1287 OUUWUAPPLICATIS I FOR ATIO“+” Input Settling resistance must be used, the sample time can be increased The input capacitor is switched onto the “+” input during by using a slower CLK frequency. With the minimum the sample phase (t possible sample time of 6.0µs, R SMPL, see Figures 8a, 8b and 8c). The SOURCE+ < 4.0k and C1 sample period can be as short as t < 20pF will provide adequate settle time. WHCS + 0.5 CLK cycle or as long as tWHCS + 1.5 CLK cycles before a conversion starts. This variability depends on where CS falls relative “–” Input Settling to CLK. The voltage on the “+” input must settle completely At the end of the sample phase the input capacitor switches within the sample period. Minimizing RSOURCE+ and C1 to the “–” input and the conversion starts (see Figures 8a, will improve the settling time. If large “+” input source 8b and 8c). During the conversion, the “+” input voltage is “+” and “–” Input Settling Windows tWHCS CS CLK tSUCS tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 B10 B9 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1287 F8a Figure 8a. Setup Time (tSUCS) is Met tWHCS CS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 B10 B9 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1287 F8b Figure 8b. Setup Time (tSUCS) is Met 1287fa 10
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