Datasheet ADA4857-1, ADA4857-2 (Analog Devices) - 3

Data Sheet ADA4857-1/ADA4857-2 SPECIFICATIONS ±5 V SUPPLY
TA = 25°C, G = 2, RG = RF = 499 Ω, RS = 100 Ω for G = 1 (SOIC), RL = 1 kΩ to ground, PD = no connect, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE –3 dB Bandwidth (LFCSP/SOIC) Gain (G) = 1, VOUT = 0.2 V p-p 650 850/750 MHz G = 1, VOUT = 2 V p-p 600/550 MHz G = 2, VOUT = 0.2 V p-p 400/350 MHz Full Power Bandwidth G = 1, VOUT = 2 V p-p, THD < −40 dBc 110 MHz Bandwidth for 0.1 dB Flatness G = 2, VOUT = 2 V p-p, RL = 150 Ω 75/90 MHz (LFCSP/SOIC) Slew Rate (10% to 90%) G = 1, VOUT = 4 V step 2800 V/μs Settling Time to 0.1% G = 2, VOUT = 2 V step 15 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion f = 1 MHz, G = 1, VOUT = 2 V p-p (HD2) −108 dBc f = 1 MHz, G = 1, VOUT = 2 V p-p (HD3) −108 dBc f = 10 MHz, G = 1, VOUT = 2 V p-p (HD2) −88 dBc f = 10 MHz, G = 1, VOUT = 2 V p-p (HD3) −93 dBc f = 50 MHz, G = 1, VOUT = 2 V p-p (HD2) −65 dBc f = 50 MHz, G = 1, VOUT = 2 V p-p (HD3) −62 dBc Input Voltage Noise f = 100 kHz 4.4 nV/√Hz Input Current Noise f = 100 kHz 1.5 pA/√Hz DC PERFORMANCE Input Offset Voltage ±2 ±4.5 mV TMIN to TMAX ±7.2 mV Input Offset Voltage Drift TMIN to TMAX 2.3 22 μV/°C Input Bias Current −2 −3.3 μA TMIN to TMAX −3.8 μA Input Bias Offset Current 50 800 nA Open-Loop Gain VOUT = −2.5 V to +2.5 V 57 dB PD (POWER-DOWN) PIN PD Input Voltage Chip powered down ≥ (+VS − 2) V Chip powered down, TMIN to TMAX ≥ (+VS − 1.7) V Chip enabled ≤ (+VS − 4.2) V Chip enabled, TMIN to TMAX ≤ (+VS – 5.3) V Turn-Off Time 50% off PD to <10% of final VOUT, VIN = 1 V, G = 2 55 μs Turn-On Time 50% off PD to <10% of final VOUT, VIN = 1 V, G = 2 33 ns PD Pin Leakage Current Chip enabled 58 μA Chip powered down 80 μA INPUT CHARACTERISTICS Input Resistance Common mode 8 MΩ Differential mode 4 MΩ Input Capacitance Common mode 2 pF Input Common-Mode Voltage ±4 V Range Common-Mode Rejection Ratio VCM = ±1 V −78 −86 dB VCM = −3.6 V to +3.7 V, TMIN to TMAX −70 dB Rev. D | Page 3 of 21 Document Outline FEATURES APPLICATIONS CONNECTION DIAGRAMS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ±5 V SUPPLY +5 V SUPPLY ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS APPLICATIONS INFORMATION POWER-DOWN OPERATION CAPACITIVE LOAD CONSIDERATIONS RECOMMENDED VALUES FOR VARIOUS GAINS ACTIVE LOW-PASS FILTER (LPF) NOISE CIRCUIT CONSIDERATIONS PCB LAYOUT POWER SUPPLY BYPASSING GROUNDING OUTLINE DIMENSIONS ORDERING GUIDE