Datasheet MCP601, MCP601R, MCP602, MCP603, MCP604 (Microchip) - 9

MCP601/1R/2/3/4 Note:
Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
5.0 5.0 V V 4.5 DD = 5.0V 4.5 DD = 5.0V G = +1 G = –1 4.0 4.0 3.5 3.5 e (V) g 3.0 3.0 age (V) lta lt o 2.5 o 2.5 V 2.0 2.0 1.5 tput u 1.5 Output V 1.0 O 1.0 0.5 0.5 0.0 0.0 Time (1 µs/div) Time (1 µs/div) FIGURE 2-25:
Large Signal Non-Inverting
FIGURE 2-28:
Large Signal Inverting Pulse Pulse Response. Response.
VDD = 5.0V VDD = 5.0V ) G = +1 ) G = –1 mV/div mV/div e (20 g e (20 g lta o lta o Output V Output V Time (1 µs/div) Time (1 µs/div) FIGURE 2-26:
Small Signal Non-Inverting
FIGURE 2-29:
Small Signal Inverting Pulse Pulse Response. Response.
5.5 0 V 5.0 DD = 5.5V CS -100 ) 4.5 V (V DD = 5.0V nt -200 4.0 G = +1 re 3.5 (µA) V -300 IN = 2.5V SS 3.0 Cur R -400 2.5 L = 100 kΩ to GND ent ct Voltage 2.0 V sc -500 put Voltage, le OUT Active e ie 1.5 u through V -600 Out Q 1.0 -700 Chip S 0.5 0.0 V -800 OUT High-Z -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Time (5 µs/div) Chip Select Voltage (V) FIGURE 2-27:
Chip Select Timing
FIGURE 2-30:
Quiescent Current Through (MCP603). VSS vs. Chip Select Voltage (MCP603). © 2007 Microchip Technology Inc. DS21314G-page 9 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: MCP603 Chip Select (CS) Timing Diagram. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-2: Slew Rate vs. Temperature. FIGURE 2-3: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-4: Quiescent Current vs. Supply Voltage. FIGURE 2-5: Quiescent Current vs. Temperature. FIGURE 2-6: Input Noise Voltage Density vs. Frequency. FIGURE 2-7: Input Offset Voltage. FIGURE 2-8: Input Offset Voltage vs. Temperature. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.7V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: CMRR, PSRR vs. Temperature. FIGURE 2-12: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-13: Channel-to-Channel Separation vs. Frequency. FIGURE 2-14: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-15: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-16: CMRR, PSRR vs. Frequency. FIGURE 2-17: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Supply Voltage. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-22: DC Open-Loop Gain vs. Temperature. FIGURE 2-23: Output Voltage Headroom vs. Temperature. FIGURE 2-24: Output Short-Circuit Current vs. Supply Voltage. FIGURE 2-25: Large Signal Non-Inverting Pulse Response. FIGURE 2-26: Small Signal Non-Inverting Pulse Response. FIGURE 2-27: Chip Select Timing (MCP603). FIGURE 2-28: Large Signal Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Quiescent Current Through VSS vs. Chip Select Voltage (MCP603). FIGURE 2-31: Chip Select Pin Input Current vs. Chip Select Voltage. FIGURE 2-32: Hysteresis of Chip Select’s Internal Switch. FIGURE 2-33: The MCP601/1R/2/3/4 family of op amps shows no phase reversal under input overdrive. FIGURE 2-34: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table For Single Op Amps TABLE 3-2: Pin Function Table For Dual And Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 MCP603 Chip Select 4.4 Capacitive Loads FIGURE 4-4: Output resistor RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO values for capacitive loads. 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring layout. 4.8 Typical Applications FIGURE 4-8: Second-Order, Low-Pass Sallen-Key Filter. FIGURE 4-9: Second-Order, Low-Pass Multiple-Feedback Filter. FIGURE 4-10: Three-Op Amp Instrumentation Amplifier. FIGURE 4-11: Two-Op Amp Instrumentation Amplifier. FIGURE 4-12: Photovoltaic Mode Detector. FIGURE 4-13: Photoconductive Mode Detector. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulatior Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information