Datasheet OP177 (Analog Devices)

Ultraprecision Operational Amplifier Data Sheet OP177 FEATURES PIN CONFIGURATION Ultralow offset voltage V 1 8 T OS TRIM VOS TRIM OP177 A = 25°C, 25 μV maximum –IN 2 7 V+ Outstanding offset voltage drift 0.3 μV/°C maximum +IN 3 6 OUT Excellent open-loop gain and gain linearity TOP VIEW V– 4 5 NC 12 V/μV typical
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(Not to Scale) CMRR: 130 dB minimum NC = NO CONNECT
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PSRR: 115 dB minimum
Figure 1. 8-Lead PDIP (P-Suffix), 8-Lead SOIC (S-Suffix)
Low supply current 2.0 mA maximum Fits industry-standard precision operational amplifier sockets GENERAL DESCRIPTION
The OP177 features one of the highest precision performance of This low noise, bipolar input operational amplifier is also a cost any operational amplifier currently available. Offset voltage of the effective alternative to chopper-stabilized amplifiers. The OP177 OP177 is only 25 μV maximum at room temperature. The ultralow provides chopper-type performance without the usual problems VOS of the OP177 combines with the exceptional offset voltage of high noise, low frequency chopper spikes, large physical size, drift (TCVOS) of 0.3 μV/°C maximum to eliminate the need for limited common-mode input voltage range, and bulky external external VOS adjustment and increases system accuracy over storage capacitors. temperature. The OP177 is offered in the −40°C to +85°C extended industrial The OP177 open-loop gain of 12 V/μV is maintained over the full temperature ranges. This product is available in 8-lead PDIP, as ±10 V output range. CMRR of 130 dB minimum, PSRR of 120 dB well as the space saving 8-lead SOIC. minimum, and maximum supply current of 2 mA are just a few examples of the excellent performance of this operational amplifier. The combination of outstanding specifications of the OP177 ensures accurate performance in high closed-loop gain applications.
FUNCTIONAL BLOCK DIAGRAM V+ (OPTIONAL NULL) R R 2A* 2B* C1 R7 R R 1A 1B 2B Q19 Q Q 9 10 R9 Q Q Q11 Q12 7 8 Q Q 5 3 Q Q OUTPUT 6 4 R3 C C Q NONINVERTING Q 3 2 17 27 R10 Q INPUT Q 16 1 R Q 5 26 Q21 Q23 Q20 Q25 R Q Q 4 22 24 INVERTING Q Q 15 2 INPUT Q Q 18 14 Q13 R R 6 8 V–
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*R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.
00289- Figure 2. Simplified Schematic
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Document Outline FEATURES PIN CONFIGURATION GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TEST CIRCUITS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GAIN LINEARITY THERMOCOUPLE AMPLIFIER WITH COLD-JUNCTION COMPENSATION PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER ISOLATING LARGE CAPACITIVE LOADS BILATERAL CURRENT SOURCE PRECISION ABSOLUTE VALUE AMPLIFIER PRECISION POSITIVE PEAK DETECTOR PRECISION THRESHOLD DETECTOR/AMPLIFIER OUTLINE DIMENSIONS ORDERING GUIDE