Datasheet Texas Instruments SN74LVTH18512 — Даташит

Производитель	Texas Instruments
Серия	SN74LVTH18512

Datasheets

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Статус

Корпус / Упаковка / Маркировка

Параметры

Parameters / Models	74LVTH18512DGGRE4	SN74LVTH18512DGGR
Bits	18	18
F @ Nom Voltage(Max), Mhz	160	160
ICC @ Nom Voltage(Max), мА	24	24
Рабочий диапазон температур, C	от -40 до 85	от -40 до 85
Output Drive (IOL/IOH)(Max), мА	64/-32	64/-32
Package Group	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	64TSSOP: 138 mm2: 8.1 x 17(TSSOP)	64TSSOP: 138 mm2: 8.1 x 17(TSSOP)
Rating	Catalog	Catalog
Technology Family	LVT	LVT
VCC(Max), В	3.6	3.6
VCC(Min), В	2.7	2.7
Voltage(Nom), В	3.3	3.3
tpd @ Nom Voltage(Max), нс	4.9	4.9

Экологический статус

Application Notes

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  Programming CPLDs Via the 'LVT8986 LASP
  PDF, 819 Кб, Файл опубликован: 1 ноя 2005
  This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
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  LVT Family Characteristics (Rev. A)
  PDF, 98 Кб, Версия: A, Файл опубликован: 1 мар 1998
  To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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  LVT-to-LVTH Conversion
  PDF, 84 Кб, Файл опубликован: 8 дек 1998
  Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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  Bus-Hold Circuit
  PDF, 418 Кб, Файл опубликован: 5 фев 2001
  When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
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  16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
  PDF, 895 Кб, Версия: B, Файл опубликован: 22 май 2002
  TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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  Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
  PDF, 105 Кб, Версия: A, Файл опубликован: 1 авг 1997
  The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
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  Understanding Advanced Bus-Interface Products Design Guide
  PDF, 253 Кб, Файл опубликован: 1 май 1996
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  Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
  PDF, 209 Кб, Файл опубликован: 10 май 2002
  Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
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  Input and Output Characteristics of Digital Integrated Circuits
  PDF, 1.7 Мб, Файл опубликован: 1 окт 1996
  This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou

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Классификация производителя

• Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic