Datasheet Texas Instruments SN74GTLP1394PWR — Даташит
| Производитель | Texas Instruments |
| Серия | SN74GTLP1394 |
| Модель | SN74GTLP1394PWR |
2-битная шина Xcvr от LVTTL к GTLP с регулируемой скоростью по краям с разделенным портом LVTTL, каналом обратной связи и выбираемой полярностью 16-TSSOP от -40 до 85
Datasheets
SN74GTLP1394 datasheet
PDF, 882 Кб, Версия: F, Файл опубликован: 25 апр 2003
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Цены
 Купить SN74GTLP1394PWR на РадиоЛоцман.Цены — от 15 до 402 ₽25 предложений от 12 поставщиков 2Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Selectable Polarity 16-TSSOP -40℃ to 85℃ | |||
| SN74GTLP1394PWR Texas Instruments | от 15 ₽ | ||
| SN74GTLP1394PWR Texas Instruments | 133 ₽ | ||
| SN74GTLP1394PWR Texas Instruments | от 380 ₽ | ||
| SN74GTLP1394PWR Texas Instruments | по запросу | ||
Статус
| Статус продукта | В производстве (Рекомендуется для новых разработок) |
| Доступность образцов у производителя | Да |
Корпус / Упаковка / Маркировка
| Pin | 16 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Маркировка | GP394 |
| Width (мм) | 4.4 |
| Length (мм) | 5 |
| Thickness (мм) | 1 |
| Pitch (мм) | .65 |
| Max Height (мм) | 1.2 |
| Mechanical Data | Скачать |
Параметры
| Bits | 2 |
| F @ Nom Voltage(Max) | 175 Mhz |
| ICC @ Nom Voltage(Max) | 20 мА |
| Рабочий диапазон температур | от -40 до 85 C |
| Output Drive (IOL/IOH)(Max) | 100 мА |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | GTLP |
| VCC(Max) | 3.45 В |
| VCC(Min) | 3.15 В |
| Voltage(Nom) | 3.3 В |
| tpd @ Nom Voltage(Max) | 8.6 нс |
Экологический статус
| RoHS | Совместим |
Application Notes
- Texas Instruments GTLP Frequently Asked QuestionsPDF, 496 Кб, Файл опубликован: 1 янв 2001
Using a question-and-answer format, advantages of TI?s GTLP devices, particularly for backplane applications, are presented, as well as differences between GTLP and GTL/LVDS devices. Applicable topics include data throughput rates, synchronous clocks, price and alternative sources, bus transceivers, live insertion, power consumption, backplane termination, voltage translation, IBIS and HSPICE mode - Logic in Live-Insertion Applications With a Focus on GTLPPDF, 493 Кб, Файл опубликован: 14 янв 2002
Live-insertion capability is an essential part of today?s high-speed data systems because those systems are expected to run continuously without being powered down. This application report delves into the cause and prevention of live-insertion and nanosecond-discontinuity effects, using both simulation and actual test measurements from a specially built GTLP EVM. Hypothetical cases for precharge c - Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)PDF, 585 Кб, Файл опубликован: 5 апр 2001
This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines, key factors that influence the bus line delay, and the impedance of bus lines are described.The theoretical - Fast GTLP Backplanes With the GTLPH1655 (Rev. A)PDF, 1.1 Мб, Версия: A, Файл опубликован: 19 сен 2000
This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OECE circuitry and implementation of theTexas Instruments TI-OPCE circuitry, that have been incorporated in the GTLPH1655 device. These improvements significantly improve signal integrity in distributed loads.This application report describes the physical principles of fast - Power-Up 3-State (PU3S) Circuits in TI Standard Logic DevicesPDF, 209 Кб, Файл опубликован: 10 май 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
Модельный ряд
Серия: SN74GTLP1394 (5)
- SN74GTLP1394D SN74GTLP1394DR SN74GTLP1394PW SN74GTLP1394PWR SN74GTLP1394PWRE4
Классификация производителя
- Semiconductors > Logic > Backplane Logic (GTL/TTL/BTL/ECL Transceiver/Translator)
