Datasheet Texas Instruments ADS5422 — Даташит
| Производитель | Texas Instruments |
| Серия | ADS5422 |
14-битный аналого-цифровой преобразователь (АЦП) со скоростью 62 MSPS
Datasheets
14-Bit, 62MSPS Sampling Analog-To-Digital Converter datasheet
PDF, 994 Кб, Версия: D, Файл опубликован: 22 июн 2005
Выписка из документа
Цены
 Купить ADS5422 на РадиоЛоцман.Цены — от 4 524 до 31 760 ₽20 предложений от 16 поставщиков Аналого-цифровые преобразователи (АЦП) 14-Bit 62MSPS Sampling ADC | |||
| ADS5422Y/250 Texas Instruments | 4 524 ₽ | ||
| ADS5422Y/250 Texas Instruments | 6 328 ₽ | ||
| ADS5422EVM Texas Instruments | 31 760 ₽ | ||
| ADS5422EVM Texas Instruments | по запросу | ||
Статус
| ADS5422Y/250 | |
|---|---|
| Статус продукта | В производстве |
| Доступность образцов у производителя | Нет |
Корпус / Упаковка / Маркировка
| ADS5422Y/250 | |
|---|---|
| N | 1 |
| Pin | 64 |
| Package Type | PM |
| Industry STD Term | LQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Маркировка | ADS5422Y |
| Width (мм) | 10 |
| Length (мм) | 10 |
| Thickness (мм) | 1.4 |
| Pitch (мм) | .5 |
| Max Height (мм) | 1.6 |
| Mechanical Data | Скачать |
Параметры
| Parameters / Models | ADS5422Y/250 |
|---|---|
| # Input Channels | 1 |
| Analog Input BW, МГц | 300 |
| Архитектура | Pipeline |
| DNL(Max), +/-LSB | 1 |
| DNL(Typ), +/-LSB | 0.65 |
| ENOB, Bits | 11.7 |
| INL(Typ), +/-LSB | 4 |
| Input Buffer | No |
| Input Range, Vp-p | 2,4 |
| Interface | Parallel LVDS |
| Рабочий диапазон температур, C | от -40 до 85 |
| Package Group | LQFP |
| Package Size: mm2:W x L, PKG | 64LQFP: 144 mm2: 12 x 12(LQFP) |
| Power Consumption(Typ), mW | 1200 |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Разрешение, Bits | 14 |
| SFDR, дБ | 85 |
| SINAD, дБ | 72 |
| SNR, дБ | 72 |
| Sample Rate(Max), MSPS | 62 |
Экологический статус
| ADS5422Y/250 | |
|---|---|
| RoHS | Совместим |
Application Notes
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Кб, Версия: A, Файл опубликован: 18 май 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Кб, Версия: B, Файл опубликован: 9 окт 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Кб, Версия: A, Файл опубликован: 10 сен 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Мб, Версия: A, Файл опубликован: 19 июл 2013
- CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Кб, Файл опубликован: 8 июн 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Мб, Версия: A, Файл опубликован: 22 май 2015
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Кб, Версия: A, Файл опубликован: 16 апр 2015
- High-Speed Analog-to-Digital Converter BasicsPDF, 1.1 Мб, Файл опубликован: 11 янв 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Кб, Файл опубликован: 28 апр 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
Модельный ряд
Серия: ADS5422 (1)
Классификация производителя
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
