Datasheet Texas Instruments TMS320C6474FGUN2 — Даташит

Производитель	Texas Instruments
Серия	TMS320C6474
Модель	TMS320C6474FGUN2

Datasheets

Цены

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Статус

Корпус / Упаковка / Маркировка

Параметры

Экологический статус

Комплекты разработчика и оценочные наборы

• Development Kits: TMDSEVM6472
  TMS320C6472 Evaluation Module
  Статус продукта: В производстве (Рекомендуется для новых разработок)
  
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• JTAG Emulators/ Analyzers: TMDSEMU200-U
  XDS200 USB Debug Probe
  Статус продукта: В производстве (Рекомендуется для новых разработок)
  
• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
  XDS560v2 System Trace USB & Ethernet Debug Probe
  Статус продукта: В производстве (Рекомендуется для новых разработок)
  
• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
  XDS560v2 System Trace USB Debug Probe
  Статус продукта: В производстве (Рекомендуется для новых разработок)
  

Application Notes

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  TMS320C6474 Multicore Digital Signal Processor Technical Brief
  PDF, 288 Кб, Файл опубликован: 14 окт 2008
  The TMS320C6474 DSP integrates three 1-GHz C64x+ DSP CPU cores, a host of high-speed peripherals, and large amounts of internal memory in a compact 23 mm by 23 mm package. These features allow the C6474 device to provide significant performance integration and high-performance density, along with substantial efficiencies in power, cost, and board space.
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  TMS320C6474 Power Consumption Summary
  PDF, 85 Кб, Файл опубликован: 14 окт 2008
  This document discusses the power consumption of the Texas Instruments TMS320C6474 digital signal processor (DSP). The power consumption on the TMS320C6474 device is highly application-dependent; therefore, a power spreadsheet that estimates power consumption is provided along with this application report. This spreadsheet can be used to model power consumption for user applications such as power
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  TMS320C6474 Module Throughput Application Report
  PDF, 140 Кб, Файл опубликован: 14 окт 2008
  This document provides information on the C6474 module throughput.
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  Direct I/O Library
  PDF, 30 Кб, Файл опубликован: 28 авг 2009
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute, visit this topic at:http://www.tiexpressdsp.com/index.php/DIO_LibraryThis DIO library aims at providing a CSL-like Serial RapidIO (SRIO) functional layer for the directIO mode of Texas Instruments' TMS320C64
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  TMS320C6474 SERDES Implementation Guidelines
  PDF, 127 Кб, Файл опубликован: 14 окт 2008
  This document contains implementation instructions for the three serializer/deserializer (SERDES) based interfaces on the TMS320C6474 DSP device. These include the Serial RapidIOВ® (SRIO), antenna, and serial gigabit media independent interface (SGMII) interfaces.Serial RapidIO is an industry-standard high-speed switched-packet interconnect. The antenna interface is compatible with two industr
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  TMS320C6474 Hardware Design Guide (Rev. B)
  PDF, 381 Кб, Версия: B, Файл опубликован: 3 авг 2010
  This document describes hardware system design considerations for the TMS320C6474 device.
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  Connecting Antenna Interface (AIF) With TDM Bridge Chip (IDT 80HFC001)
  PDF, 28 Кб, Файл опубликован: 28 авг 2009
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute, visit this topic at:http://tiexpressdsp.com/index.php/AIFThis article was designed for both beginners and advanced users of the Antenna Interface in the embedded processor TMS320C6474 chip support software library. It i
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  TMS320C6474 DDR2 Implementation Guidelines (Rev. A)
  PDF, 96 Кб, Версия: A, Файл опубликован: 4 авг 2009
  This document provides implementation instructions for the DDR2 interface contained on the C6474 DSP device.
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  Inter-Core Communication on TMS320C6474
  PDF, 961 Кб, Файл опубликован: 12 янв 2009
  Inter-core (also called Inter-CPU or Inter-Processor) communication on the C6474 multi-core DSP devices can be accomplished using the on-chip inter-processor communication (IPC) module. The main function of the IPC module is to provide inter-core interrupts. Optionally, flags can be sent along with an interrupt for implementation or more advanced inter-core communication protocols.The purpose o
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  Using the TMS320C6474 Antenna Interface (AIF) for Inter-DSP Communication
  PDF, 27 Кб, Файл опубликован: 28 авг 2009
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute, visit this topic at:href=http://wiki.davincidsp.com/index.php/AIF_Inter_DSP_CommunicationThe TMS320C6474 Antenna Interface (AIF) is a CPRI and OBSAI-compliant peripheral whose primary purpose
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  TMS320C6474 Common Bus Architecture (CBA) Throughput
  PDF, 73 Кб, Файл опубликован: 14 окт 2008
  This application report presents common bus architecture protocols and components as main factors for generic throughput analysis. It provides necessary details on the internal bus structure which enables you to estimate system-on-chip (SoC) performance for a given application.
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  How to Approach Inter-Core Communication on TMS320C6474
  PDF, 142 Кб, Файл опубликован: 27 янв 2009
  Today's digital signal processor (DSP) architectures are confronted with the tough requirement of addressing a wide-range of standards and meeting a cost-effective performance/power trade-off. Increasing raw million instructions per second (MIPS) performance just by running at a higher frequency is not possible anymore since leakage is becoming a dominant factor with shrinking silicon geometries.
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  TPS40197 Reference Design
  PDF, 614 Кб, Файл опубликован: 17 дек 2008
  The TPS40197 reference design is a synchronous buck converter providing VID programmable output voltage from 0.9 V to 1.2 V at up to 7 A from a 12-V or 5-V bus (4.75 V ~ 13.2 V). The design uses the TPS40197 – a synchronous buck controller with 4-bit VID interface for Smart-Reflex™ DSPs.
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  C6474 (x2) Power Using Modules
  PDF, 107 Кб, Файл опубликован: 30 сен 2008
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  C6474 (x4) Power Using Modules
  PDF, 131 Кб, Файл опубликован: 1 окт 2008
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  TMS320C6455 to TMS320C6474 Migration Guide
  PDF, 311 Кб, Файл опубликован: 14 окт 2008
  The TMS320C6455 fixed-point digital signal processor (DSP) and the TMS320C6474 communications infrastructure DSP are two of Texas Instruments’ high-performance DSP processors, each offering high-speed DSP processing, large internal memories, a rich set of peripherals, and other support functions useful in a system environment.This application report describes device considerations for migrati
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  Tuning VCP2 and TCP2 Bit Error Rate Performance
  PDF, 293 Кб, Файл опубликован: 11 фев 2011
  In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
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  Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A)
  PDF, 80 Кб, Версия: A, Файл опубликован: 19 июл 2013
  This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
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  Multicore Programming Guide (Rev. B)
  PDF, 1.8 Мб, Версия: B, Файл опубликован: 29 авг 2012
  As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
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  EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (Rev. A)
  PDF, 292 Кб, Версия: A, Файл опубликован: 21 авг 2008
  This application report summarizes the key differences between the enhanced direct memory access (EDMA3) used on C64x+в„ў DSP devices and the EDMA2 used on TMS320C64xв„ў DSP devices, and provides guidance for migrating from EDMA2 to EDMA3.
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  TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
  PDF, 310 Кб, Версия: A, Файл опубликован: 20 окт 2005
  This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
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  Introduction to TMS320C6000 DSP Optimization
  PDF, 535 Кб, Файл опубликован: 6 окт 2011
  The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then

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Классификация производителя

• Semiconductors > Processors > Digital Signal Processors > C6000 DSP > Other C6000 DSP