Datasheet Texas Instruments ADS5541IPAP — Даташит
| Производитель | Texas Instruments |
| Серия | ADS5541 |
| Модель | ADS5541IPAP |
14-битный аналого-цифровой преобразователь (АЦП) с быстродействием 105 MSPS 64-HTQFP от -40 до 85
Datasheets
14-Bit, 105MSPS Analog-to-Digital Converter datasheet
PDF, 1.2 Мб, Версия: C, Файл опубликован: 31 янв 2007
Выписка из документа
Цены
 Купить ADS5541IPAP на РадиоЛоцман.Цены — от 6 288 до 799 581 ₽19 предложений от 13 поставщиков Интегральные микросхемы Сбор данных — АЦП | |||
| ADS5541IPAP Texas Instruments | 6 288 ₽ | ||
| ADS5541IPAP Texas Instruments | 6 898 ₽ | ||
| ADS5541IPAP | 799 581 ₽ | ||
| ADS5541IPAP Texas Instruments | по запросу | ||
Статус
| Статус продукта | В производстве (Рекомендуется для новых разработок) |
| Доступность образцов у производителя | Нет |
Корпус / Упаковка / Маркировка
| Pin | 64 |
| Package Type | PAP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 160 |
| Carrier | JEDEC TRAY (10+1) |
| Маркировка | ADS5541I |
| Width (мм) | 10 |
| Length (мм) | 10 |
| Thickness (мм) | 1 |
| Pitch (мм) | .5 |
| Max Height (мм) | 1.2 |
| Mechanical Data | Скачать |
Параметры
| # Input Channels | 1 |
| Analog Input BW | 750 МГц |
| Архитектура | Pipeline |
| DNL(Max) | 0.25 +/-LSB |
| DNL(Typ) | 0.25 +/-LSB |
| ENOB | 11.4 Bits |
| INL(Max) | 2.5 +/-LSB |
| INL(Typ) | 2.5 +/-LSB |
| Input Buffer | No |
| Input Range | 2.3 Vp-p |
| Interface | Parallel CMOS |
| Рабочий диапазон температур | от -40 до 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 64HTQFP: 144 mm2: 12 x 12(HTQFP) PKG |
| Power Consumption(Typ) | 710 mW |
| Rating | Catalog |
| Reference Mode | Int |
| Разрешение | 14 Bits |
| SFDR | 86 дБ |
| SINAD | 72 дБ |
| SNR | 72.7 дБ |
| Sample Rate(Max) | 105 MSPS |
Экологический статус
| RoHS | Совместим |
Комплекты разработчика и оценочные наборы
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Статус продукта: В производстве (Рекомендуется для новых разработок) - Evaluation Modules & Boards: DEM-OPA-ADS-SO-1A
DEM-OPA-ADS-SO-1A
Статус продукта: Анонсирован (Компонент анонсирован, но еще не запущен в серийное производство. Образцы могут быть как доступны, так и нет)
Application Notes
- Clocking High-Speed Data ConvertersPDF, 310 Кб, Файл опубликован: 18 янв 2005
- CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Кб, Файл опубликован: 4 сен 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Мб, Версия: A, Файл опубликован: 22 май 2015
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Мб, Версия: A, Файл опубликован: 19 июл 2013
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Кб, Файл опубликован: 28 апр 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Кб, Версия: A, Файл опубликован: 10 сен 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Кб, Файл опубликован: 8 июн 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Кб, Версия: A, Файл опубликован: 16 апр 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Кб, Версия: B, Файл опубликован: 9 окт 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Кб, Версия: A, Файл опубликован: 18 май 2015
Модельный ряд
Серия: ADS5541 (1)
- ADS5541IPAP
Классификация производителя
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
